1130 MRAM testing observations while I wait for the new board for the updated design

PCB AND PARTS ARRIVING ON MONDAY

I had redesigned the board to utilize an FPGA to drive all the timing, dropping the use of timer chips and simple combinatorial logic. The FPGA code was developed, simulated, and I loaded the bitstream into the new Digilent CMOD S7 board that will be installed of my new PCB.  The PCB blank and some final components are due to be delivered on Monday, so that on Tuesday I can build the new board to begin testing. 

OBSERVATIONS DOING MANUAL DISPLAY AND LOAD MODE CYCLES

When I set the rotary mode switch to Load or Display and push the Prog Start button, the 1130 takes one memory cycle and either loads memory with the value set in the Console Entry Switch (CES) toggles switches or reads the contents of the memory location and shows it on the SBR lights. 

I was able to load patterns and get reliable readback until I got over about five 1 bits in a word. At that point, some of the bits did not display correctly when read back. A pattern with four 1 bits would be reliably written and read back - this may be more than four bits because there may be parity bits in addition to the data bits that have a 1 value. 

The new design will set only three bits at a time, skewing the setting across multiple 85 ns cycle times of the FPGA. Thus whatever is causing the issue observed should not recur. 

When words with a high number of 1 bits are loaded, I would observe that when displaying, some words would come back as all zeroes while others either had the pattern or the pattern with some of the 1 bits missing. 

The final anomaly that I observed was that when resetting the 1130 using the Reset button, from time to time the value of the word at location 0 was erased instead of having its previously written value. This may be a fault caused my prior design where it reacts poorly to the instantaneous changes in signals during the reset and as the processor comes out of reset. 

Since my new design changes how the control signals are generated, now using the FPGA onboard, this issue is probably not going to recur. An advantage of having shifted to an FPGA for timing and control signals, is that I can change the behavior with changes to Verilog code and update the FPGA board without requiring hardware changes.