Side project - MV864A restoration - reverse engineering power supply section

 WAITING ON PCB AND PARTS TO RESUME MAINSTREAM 1130 ACTIVITIES

The 1130MRAM memory PCB is scheduled to arrive on October 10th and the new components will be here on the 8th. Until I have the new board ready to final testing on the 1130, it does not have working core memory. That is required to begin testing the 1132 printer and 2501 card reader controller logic as well as to resume testing of my virtual 2315 disk cartridge project. 

In the interim I will keep busy doing these side projects - the Millivac MV864A meter and the IBM 3278 terminal restorations for example. It was worth $28 to speed up the delivery of the PCB, since I am eager to work on the top priority 1130 restoration tasks. 

POWER SUPPLY VASTLY DIFFERENT FROM THE MANUAL AND SCHEMATIC

The manual shows a power supply with four silicon transistors, four diodes, a zener diode, an LED for the main power indicator and three test points to measure +8.5V, -6V and ground. The actual board in my meter has one transistor-like device plus a large germanium power transistor, two diodes, and an incandescent main power indicator. 

Even odder, the three test points I found, marked TP63, TP62, and ground, measure -14.5V, -6V and 0V respectively. There is an 8.5V delta between the first two, but nothing shows up as +8.5V. The meter appears to work, thus this must not be a result of failure in the supply. Rather this is likely due to the older germanium technology used on my meter versus the redesign with silicon semiconductors. 

CHALLENGES FINDING DATASHEETS FOR BOTH TRANSISTOR DEVICES

I have completely failed to find any data sheets for the MHT3030 power transistor, although it is almost certainly a germanium PNP device. I did find the smaller device, a General Electric RA-1, in an old GE manual found on the web. It is a compound device, four terminal, with a transistor plus a zener diode attached to the transistor emitter. It was used in voltage regulator circuits and there are reference designs in the GE manual. 

This manual "GE Transistor Manual - Circuits, Applications, Characteristics, Theory" published in 1964 is a gold mine of information. The section on Regulated DC Supply and Inverter Circuits covers the Reference Amplifier (RA) devices and circuits using them to build 'precision' voltage regulators. Here is the sample circuit in the manual:

This corresponds extremely well with the recovered design from my reverse engineering. A few differences - the meter uses a half wave rectifier rather than the full wave design from the GE manual and the GE manual uses a fixed resistor voltage divider to provide the 7V reference voltage to the RA1 base when the output is (almost) 12V. 

Due to resistor tolerances and a more limited choice of resistor values in the 1960s, GE chose the resistors to give 11.73V which was the close enough (for a 'precision' voltage regulator). The inclusion of a potentiometer in the Millivac circuit allows for adjustment to hit a target output voltage, with the midpoint of the pot setting -14V and enough range to achieve -14.5V. 

Here is the schematic I created from reverse engineering the board of my meter:

Two things remain a mystery to me after this work. First, the method of creating -6V appears to be a simple voltage drop over 540 ohms of resistance - this only works out to an 8.5V delta if the current through the resistors is 15.7ma. Until I see how this line is connected on the other PCB I can't assess whether this makes sense.  Second, the existence of -14.5V and -6V rather than the +8.5V and -6V of the manual's power supply. 

Here is the schematic from the manual for comparison:

Side project - MV864A restoration - reverse engineering challenge

PICKED UP MILLIVAC MV864A AND PAID FOR MANUAL FROM THE MANUFACTURER

Having purchased a used high accuracy meter on eBay, it was time to restore and calibrate it so that I can use it on my bench. It generally works, but when I used my bench power supplies to deliver given voltages and currents to compare with the meter reading. The readings were close but not exactly on. 

This meter has a grid of potentiometers on the rear which allow for calibration of each scale of voltage, current and resistance. I found that on some ranges I couldn't get the meter all the way to the target reading even at the extreme of the pot movement. I also didn't know if I had to do the calibrations in a certain sequence or could adjust any scale independently of the others. 

I contacted Millivac and asked if I could buy the manual that has the schematic and calibration instructions. I provided the serial number of the unit to have them find the proper version of the manual. I was told that the oldest manual they could provide was for a newer version but that the schematics and other information should be quite close. I spent the $100 and began the restoration when it arrived - see earlier posts about this side project for details. 

MAJOR DISSONANCE BETWEEN MANUAL AND THE UNIT ON HAND

Unfortunately for me, the schematics and other diagrams are very different - you can see that the general scheme is the same but the parts used and layout were very, very different. The major reason is that my unit uses primarily germanium transistors whereas the manual shows the meter after they had re-engineered this around silicon transistors.

The parts numbers are all different, because it was a redesign. The layout on printed circuit boards is different. In order to put a scope or voltmeter on various points to compare against the values shown in the manual, you need to know where the point sits. Further, the waveforms and voltages likely have changed between the germanium and silicon designs. 

Here is the portion of the schematic that I have been reverse engineering - I still have a few values to add to the drawings and some cross checking, but it is close. First, the portion of the schematic from the manual. 

Next is the version I captured from the actual unit:

Lets zoom in one two sections to see how different they are. First we will look at the input filter that sharply notches powerline noise. Second we look at the preamplifier that finds the difference signal between the filtered input and a reference signal from the photocells of the chopper. 

For the input filter, I have the following component values and connections:

Compare that to the schematic portion from the manual. These parts should be very close since a notch filter has component values determined by the frequencies and rolloffs, which wouldn't depend on germanium versus silicon techology at all. In other words, this is the best situation for a match.

Even here we have a few discrepancies in the values of parts although most are close. The output resistance is much higher, which may be based on the change in transistor technology. The parts for the filter are visible on the board:

The variations would be tolerable here, even if I had to map out that 3R1 on the manual schematic is R201 on my PCB. Once I move into the areas where the redesign is more substantial, this becomes less feasible. 

The preamplifier as I found it on the unit has a germanium FET and two germanium 2N414 NPN transistors. 

The manual has a more complex circuit with the same FET but three silicon 2N2907 NPN transistors. I am guessing that they chose a lower gain for the three stages to achieve the same result as the two germanium transistors provided on my unit.

DIVERGENCE IS WIDENING AFTER THIS POINT

There are ten silicon transistors on the rest of the schematic and two coupling transformers in the version in the purchased manual. However, on the actual unit, there are fifteen silicon transistors and four coupling transformers. A second adjusting potentiometer is on my board, but not in the manual; it has no marking on the PCB to hint at its purpose. 

Here is the top of the PCB with the previously discussed sections partially covered to show the remaining components that must be reverse engineered. 

REVERSE ENGINEERING IS TEDIOUS BUT STRAIGHTFORWARD

The huge advantage I have is that the PCBs in the unit are single sided - traces only on the bottom and components only on the top. I have flipped the picture of the bottom so that I can match it to the parts in the top picture, allowing me to figure out the wiring between parts. 

I will keep at this until I have the entire schematic of this PCB captured. I figure I can use LT Spice to figure out the corresponding voltage and waveform values I should see at the reference points to correspond to the ones marked on the manual's schematic. 

In addition to this PCB, there is a second PCB that has the power supply and range attenuator components. This also is different from the manual version. Therefore I have to reverse engineer at least the power supply portion. The range attenuator and the front panel selector switch should match up fairly closely, so I won't bother drawing that out unless I run into problems during restoration that indicate a divergence. 

Testing the 1130 MRAM core memory replacement on the IBM 1130 system - part 4

CHANGED SENSE OUTPUT DRIVER GATE TEMPORARILY

I am resigned to having to build another PCB in order to use a chip that has enough current sink capability to work with the 1130. I did set up components on a breadboard to redrive the signal for a couple of sense lines, to see if things work correctly with sufficient current sinking.

Since the current circuit is failing to set the B register, it is the same as when I store a 0 value for that bit. I will wire up the two check bits, as they must be on with an even parity such as all zeroes. I will also wire up bit 15 so that I can experiment with setting the word to either 0000 or 0001 which both should have correct parity when read back given the three circuits I will establish.

In order to use the existing board for this test, I just lifted the output pin of the three signals off of the 74HC03 chip where they were soldered. I can tack a wire to the pad and another to the lifted pin, interposing my ad hoc circuit between the two.

I used a 74HC04 inverter chip to convert the output of the 74HC03, an open collector that pulls to ground when the pulse should be generated, to a pulse that starts at 0V and goes up to the 3.3V level for a short period. This required a pull-up resistor on the input to the inverter, pulling it to 3.3V unless the open collector sinks down to ground for the pulse. The input to the inverter comes from the 74HC03 lifted output pin.

The output of the inverter was connected through a 720 ohm resistor to a 2n3904 NPN transistor. The emitter is connected to ground, the base connected through the 720 ohm resistor and the collector is hooked to the output for the -Sense bit line. This should be capable of sinking as much current as the SLT circuit can deliver - with the resistor I selected and the gain (beta) of the 2n3904, it could sink around 180ma which is why more than the 8-9ma I see in the LTSpice simulation as a minimum to flip and the 24ma it shows when the transistor is saturated. 

TESTING WITH LOAD AND DISPLAY MODE

I did a load of memory with all zero bits, then did a display. This should return all zeroes plus the two parity check bits at 1, for a good read. This worked as expected, no parity stop. The pulse coming back from the sense outputs to the B register were nice and strong. 

I then flipped bit 15 of the Console Entry Switches to 1 and loaded that value (x0001) to memory before doing another read. This should deliver x0001 to the 1130 with the first check bit at 1 and the second check bit at 0. That was exactly what I saw on the display panel and again no parity stop. The scope showed that the pulse was strong enough to definitively flip the B register bit on when we are outputting a pulse. 

B reg in purple set by sense pulse in blue

FIXING THE ISSUE PERMANENTLY

After I had validated the diagnosis that insufficient current sinking was the issue with the 74HC03 chips I had used on the prior design, I switched my design over to 74LCX38 chips that will sink 24ma per output, works on 3.3V VCC and is also a quad 2 input NAND open collector device. 

While an SOIC-14 version of the 74LCX38 is identical in footprint to the 74HC03, it is effectively unavailable so I had to switch to the smallest TSSOP footprint as even the intermediate SOP version was effectively unavailable. That required me to redo the PCB which I completed and sent off to JLCPCB on October 3rd. I also ordered the new chips and other parts from Digikey to build the new PCB, which should arrive before the PCB.

Testing the 1130 MRAM core memory replacement on the IBM 1130 system - part 3

RESOLVED THE PIN ASSIGNMENT MISTAKE ON MY PCB

I installed jumper wires on the six pairs of pins I had previously identified. In addition, I discovered three more pairs that have the same characteristics - -Sense Bit 17, +SAR Bit 3 and +SAR Bit 10. Those were also jumpered on the backside of my board. 

TESTING WITH LOAD AND DISLAY MODE

I still saw parity errors when doing a DISPLAY on any address, but when watching the signals I could tell that I was in fact writing the 1 or 0 value into memory and then generating a pulse on the sense output line when the bit stored was a 1. 

However, B register bit was NOT being set when that pulse occurred, s it should. There is a flipflop in the B register circuitry that will be set if there is a falling edge on its input - that comes from my circuitry. 

THE ISSUE IS THE PULLDOWN CURRENT FROM MY BOARD (OR DURATION)

The sense output bit is generated by a 74HC03 gate, a NAND with open collector output where the gate pulls the output to ground when activated. The pulse may  not be long enough, at about 100 nanosecond duration, since the IBM core memory circuitry produces that pulse with a duration more like 180 ns. It is the falling edge that causes the action, not the duration, so that shouldn't matter. If it does, I could adjust it by swapping the capacitor that determines the length of the pulse I produce. 

However, what is more objectionable is the low point of the pulse I am producing. It is not down to zero volts, instead reaching no lower than about .6 volts which is way above the SLT logic zero definition. Since my gate is conducting to ground, I expected it to get much closer to 0V. 

Looking at the spec sheet for the 74HC03, it does show that with a 4.5V VCC (we are at 3.3V) and a 4ma current sunk by the gate at logic low, the voltage is typically .33V, which is already too high for SLT. As with all issue with digital logic, one has to look below the abstraction at the real analog behavior to understand why it is not switching. 

There has to be enough current to reverse the conduction of a pair of transistors at the heart of the flip-flop. This will depend on the resistors and other contributors to resistance as well as the current sink capability of the driving transistor in my gate. The flipflop is shown as consisting of several circuit elements in this IBM diagram below:

In the IBM documentation, circuit segments are named with codes such as T20SC, the first letter indicating the speed of the circuit which is 30ns in this case. The two digits define a logic function, then the suffix letters indicate the variant with differences such as resistor values used. I don't have a full set of schematics for these circuit segments but can find some (or close family members) in schematics I do have for certain SLT cards. 

This section of a 5804628 card schematic has a section where the only variance is in the two AND blocks which are S03AJ instead of S03SQ. 

The schematic for the T20xx circuits is:

The S03xx circuit attaches to one of the outer transistor collectors above such as pad 4 or 11.  On this card it uses an S03AJ circuit but we are more interested in the S03SQ which better matches our B register card. 

I then looked through other cards with flip-flops until I found the S03SQ circuit schematic on a 5803794 card:

Connector 2 above is what connects to the T20AB circuit connections to set or reset the flipflop. Connector 3 above is what connects to the output of the flipflop which blocks a set or reset from passing through if the flipflop is already in that state. Connector 6 above is the gate signal that sensitizes this circuit - when it is at logic low, a falling edge on connector 1 above will send a pulse to the flipflop. 

My board has to send a falling edge that will pull the charge from 33 pF capacitor, thus pulling down the base of a transistor in the flipflop, through a diode, causing it to conduct and flip the state. To clarify the discussion a bit, we are looking at the signals to set the flipflop when my sense bit pulse has a falling edge. 

SIMULATION TO UNDERSTAND CORRECT AND FAILING OPERATION

I set up LTSpice to simulate the circuit. I don't have exact parameters for the Germanium transistors and diodes in the IBM SLT modules, but I used a model I found for an old Germanium transistor and hoped the results would be reasonable. I set it up to be initially in the reset state and applied a 100ns pulse to the circuit on the set side at +1 second. The flipflop switched as I expected it to, seen in the graph below:

Green is Q, blue is notQ outputs of the FF

The circuit I entered is here:

I used an initial condition to set the flipflop to its correct starting state. I applied a pulse using a voltage source at the bottom and simulated to get the graph above. I can now experiment with various defects such as too high a bottom voltage for the pulse to see if I can reproduce the failure to set the flipflop. If I can, I have a way to test various solutions for correct operation. 

Without the correct diode and transistor models, I won't get the same results as I am observing but it let me explore variations in the pulse voltage dip and the pulse duration. I didn't find much sensitivity to a shorter pulse; it worked down to a 3ns duration and failed at 1ns. 

It was more sensitive to the bottom voltage of the pulse. I could get it to fail at 1.9V and work at 1.8V or lower. These aren't accurate since the semiconductors aren't accurately simulated. 

Another idea I explored is that cumulative capacitance is slowing the fall of the signal so that the duration is what limits the bottom level reached. This can be capacitance on my PCB, in the cable and in the 74HC03 chip, in addition to the backplane and receiving circuitry of the 5804619 card. I bumped the capacitor up and watched the signal closely to see whether I could reproduce the shape. Higher capacitance actually made it less sensitive. 

I then dug through my documentation for IBM SLT and found some parameters that let me refine the models for the diodes and transistors in the circuit. The new circuit with the models is:

This is modeling the shape of the pulse I am generating with my board. I found that it would fail to switch at 0.9V but switch at 0.8V or lower, much closer to the failure point I was seeing on my scope. 

dark blue is the input pulse

Even with the pulse duration extended by another 50 nanoseconds, the flip flop will not turn on when the pulse only dips to 0.85V. It is much more sensitive to the low voltage than it is to the duration of the pulse since it is edge triggered. 

I then dug into the spec sheet for the 74HC03 chip that generates the pulse and see that it is current limited compared to the demands of the flip flop edge detector. By varying the series resistance of a voltage source, I recreated the observed pulse shape with about 1K of resistance, but the flip flop needs about four times that current to flip. Interpolating the spec sheet to the 3.3V VCC I am using gets me to about 3ma of sink current, which is close to the effect of the 1K series resistance in the model. 

HAVE TO FIND NEW CHIP TO DRIVE THE SENSE OUTPUT PULSES

The simulation suggests that I need about 10-12ma of sink current to reliably flip the register on. Initially I found that a 74LVC1G138 chip provides a single 2 input NAND gate with open collector and can sink 16ma on a low output with a max of 0.4V which would be excellent if I had designed with that originally. It would require a new PCB to implement, adding more than a week of delay.

The best fit would be a chip that fits the same footprint and pinout, but sinks 12ma and operates with 3.3V VCC. The 74LCX38 chip is exactly what I want. It has the same pinout as the 74HC03, operates at 3.3V VCC, and can sink up to 24ma with a low output. It comes in an SOIC-14 narrow package that is compatible enough to solder onto my board as it is.

Now the challenge - buying the SOIC-14 version is going to be difficult. Through Digikey, I can only buy batches of chips from a marketplace dealer - Rochester.  Mouser does not carry the SOIC-14 version at all. Rochester will not sell less than $250 at a time - even though the chips are less than a dollar each. The manufacturer, OnSemi, points only at Rochester as a distributor stocking any of them. 

Of course, Amazon and eBay offer a number of vendors in China who promise they will send me the chips. In my experience, almost every vendor from China is selling fake chips - sometimes they are just marked with the part number but don't work. In other cases, they take a similar chip like the 74HC03, bleach off the identifier and remark it as the chip I want. The chip inside still won't deliver more than 3ma, so that would be a waste of money. 

Based on this, I might be forced into the PCB redesign where I have several options for chips I can buy. I guess if I can verify the design works through some Rube Goldberg adaption right now, I could finish testing on the 1130 and then order the new PCB and new chips. 

Testing the 1130 MRAM core memory replacement on the IBM 1130 system - part 2

WATCHING SIGNALS FROM THE 1130 TO THE BOARD

My first check was to watch the +StorageRead, +StorageWrite and +StorageUse signals as well as -BBit0 where I could verify that the LOAD mode of the rotary mode switch was delivering the intended bit value. 

I was missing one of the key signals, +StorageWrite,  from where I expected it to arrive. However I did see the -BBit0 signal do the right thing based on the console entry switch settings during a LOAD. 

The next test watched both a -Bbitx and a -Sensebitx line to verify their pullup to +3V when not activated. These were pulled up to 3V on the bit lines I checked.

PLUGGED IN MY BOARD, WHICH DID NOT WORK CORRECTLY

One of the symptoms was that the 1130 recorded a word with bit 10 on any time I did a DISPLAY, which flagged a parity error since my board was outputting the parity check bits based on whatever was coming out of the memory chip. These would always be correct which meant that the 1130 was detecting differently than I was outputting. 

I still had the missing +StorageWrite signal issue to contend with. I decided to test continuity of all the signals from the source gates in the CPU out to my board - all 16 -BBitx, all 16 -Sensebitx, the two parity check -Sense bits, and the three input control signals +StorageRead, +StorageWrite and +StorageUse.

CONTINUITY CHECKS OF THE SIGNALS ARRIVING ON CABLES T1, T3 and T4

The Automated Logic Diagrams (ALD) are the source I used to document the cable pins associated with each signal to the memory gate B-C1. I found discrepancies from what I expected! 

The +StorageWrite signal was only detected on cable T3 at pin J1 A11 which I had listed as a duplicate of the signal on H1 D11. When I tested the continuity between those two pins while everything was plugged into the memory compartment, they were tied together. 

However, the connection between the two could have been implemented in one of three places - the compartment holding the source gate could send its output to both pins, the cable itself would have tied the two wires together, or the memory compartment could have tied the pins together on the SLT board where the cable plugs in. 

With the cable disconnected from the destination SLT board in the memory compartment, the pins were not tied together, thus the connection was done on the memory compartment SLT board we are replacing. I chose the wrong pin of the pair that are connected in the memory compartment. 

In an ALD, the gate producing a signal has a list at the bottom of the page of every pin where the signal is connected off this ALD page. For the +StorageWrite signal, the gate producing it is AY on page MC101. The list of off page destinations was:

This only shows connections from compartment 01B-B1 where gate AY is situated to other pins on 01B-B1, not to the memory compartment. However, you need to understand that the locations in the top row of any compartment are the T1, T2, T3 and T4 cables that connect to other compartments. Looking at the cable drawing below we can see that the last two pins on the list are part of cable T3 that runs from 01B-B1 to 01B-C1 (our memory compartment. 

Thus the signal from gate AY in MC101 goes to pin H1 E11 of the memory compartment through cable T3. There it is also tied to pin J1 A11 but only on the SLT board in compartment 01B-C1 which we are replacing. I chose the wrong pin to route on my PCB. 

In addition to the control signal, which was a major error that blocked correct operation of my board for any memory access, there were five more signals where a pair of pins were tied together in the memory compartment yet I picked the wrong pin of each pair for my PCB. These are:

• -BBit0 which I assumed was B1 A09 but instead was only routed to A1 E09 on the cable
• -BBit10 which I picked from L1 A09 but was wired only to K1 E09 on the cable
• -Sense Bit 3 which I picked as B1 D11 but was wired to A1 E11 on the cable
• -Sense Bit 7 which I picked as C1 D11 but was wired to C1 A11 on the cable
• -Sense Bit 13 which I picked as L1 D11 but was wired to K1 E11 on the cable

I can tack a wire on the back of my PCB to hook the pairs of pins together as they are tied on the memory compartment SLT board, which will resolve the issues. In my defense, I saw the signal duplicated on the cable and picked the pin that fit the pattern of the others, but that was the wrong choice electrically.

You can see above how the -BBit0 and -Sense Amp Bit 3 pins I chose are in line with the others and fall into a nice pattern, while the first two instances at the top seem out of place. 

When I get back to the workshop, I will rework the back of my PCB to tie together the six pairs of pins where I chose wrongly - every single duplicate I found by the way. Then I will test again. 

Testing the 1130 MRAM core memory replacement on the IBM 1130 system - part 1

IT IS TIME TO HOOK THIS INTO THE 1130 AND TEST THERE

The three ribbon cables T1, T3 and T4 were disconnected from the gate B, compartment C1 backplane which houses the original core memory. These were inserted onto the connectors on my PCB. 

The red and black wires were connected onto the terminal strip TB2 just below gate B compartment C1 to provide the +12V power for my board. 

With that done, it was be time to power up the 1130 and check out the new memory.

TESTING ACCESS TO SOME WORDS USING THE LOAD FUNCTION

The IBM 1130 rotary mode control has a LOAD position, which uses the 16 console entry switches (CES) to input data and address values. I first set up an address on the CES then push the Load IAR button. This sets the memory address (SAR) to the chosen location. I change the CES to the data value I want to write into the chosen memory location and push the Start button on the console. This stores the value into the chosen memory location.

I put values into unique addresses using this method, then turn the rotary mode control to DISPLAY. In this mode, it reads the data in memory rather than writing it. First set up the chosen address on the CES and push Load IAR to select it. Next push the Start button to see the contents of that location display on the Storage Buffer Register (SBR) line of lights on the console.

RESULTS OF FIRST TESTS

When I attempted a DISPLAY the results were all zeroes with bad parity. I pulled out the oscilloscope to watch signals to see what is occurring. The line that I expected to see the +Storage Read signal appear was not changing. 

I will go home, review all the ALDs I have to ensure that I picked correct pins on the cables, then track down the exact issues tomorrow. I did verify that there were good voltages - +12V from the 1130 and +3.3V from the voltage regulator module - thus my board should be interacting. 

side project - IBM 3278 terminal restoration - planning for keyboard substitution

TERMINAL IS MISSING ITS ORIGINAL KEYBOARD

The 3278 terminals used the IBM beam spring type keyboards (type B), the most prized by keyboard afficionados for its feel. Thus keyboard pirates will find listings for devices like the 3278 and use only the keyboard. More often, recyclers or sellers of old gear will separate the keyboard as they can get 1-2 thousand US dollars for the keyboard itself. This leaves essentially useless terminals since the supply of keyboards has been hoovered up. 

The type B keyboard on the 3278 delivers a scan code in parallel on its interface for each key depression. These codes are associated with the position of the key-stem on the keyboard and therefore with the character printed on the keycap. 

The successor terminals like the 3178 made use of the 'type F' keyboard from IBM which is second best to the beam spring, but still desirable. Fortunately, not absurdly desirable and thus these can be found either together with their terminals or even separately for much more reasonable prices. 

The type F keyboard delivers a serial scan code, much like the later keyboards such as PS2, but the codes assigned to key-stems (and keycap characters) are different on most keys. It is feasible to read the scan code from a type M keyboard and translate that to a 3278 keyboard scan code, so that when the keycap with the character A is pressed, in the same key-stem position, the key code seen by the 3278 terminal will be the one that would have been sent by the beam spring keyboard. 

COMPLICATIONS TO DEAL WITH IN THE KEYBOARD SUBSTITUTION

The interface has wires for the seven bit scan code, power (+5, +8.5, -5, ground), power-on-reset, data available, make/break, keyboard ack, clicker, and four keyboard identifier bits. The identifier bits indicate the type of 3278 keyboard that was connected to the terminal. These include 75 and 87 key versions with different layouts. 

Many of the keys on the keyboard are called 'typeamatic', an IBM term that means if you hold the keycap down it will repeatedly emit that character, for example the space bar or a letter. Some are not. 

Some keys on the type B issue a different scan code for make (when it is pressed down) and break (when it is released) while most only issue one scan code. The type F indicates whether a keypress or a key release has occurred but we see both events. For the keys that don't have two scan codes on the type B, I can send only the make type scan code and drop the release. For those that will receive two scan codes on type B, I can map based on whether it was a make or break key action. 

There is an ALT button which changes the scan code issued for a key-stem. This only happens for the non-typeamatic keycaps; use of the Alt key involves emitting an Alt make code, the other key's scan code when it is subsequently pressed, and then the Alt break code when the Alt key is released - three scan codes emitted. 

The bottom right keycap (Enter key) is typeamatic on the type F but only emits one time no matter how long it is held down on the type B. I can resolve this by blocking repeated Enter scan code until a new character's scan code arrives from the type F. Since there is no Alt character assigned to this keystem, the fact that it is typeamatic and won't send the Alt make - Enter - Alt break sequence doesn't matter. 

The type F is a serial interface with one protocol, while the type B uses a parallel interface with a different protocol. I will need the two connector types and a microprocessor to handle the protocols on each connection, as well as handling the scan code mapping and other special handling mentioned above.