Saturday morning saw the wiring of the driver circuits to the new driver board finished up. The fourth old style interface card was completely removed, as I only used the driver circuit side of the card. At this point, all 41 outbound signals to the 1131 are wired to the new driver card with the twisted pair style ribbon cable and that card is hooked to the flat ribbon cable to the C-D side of the FPGA which controls all the output signals. It took from 8AM until almost noon, with a few short breaks to ease out the aches from hunching over doing all the wiring and soldering.
Once I wired the power connector for the new driver board into the SAC Interface box, it was time to do some short circuit testing on the new driver board connections. As well, I began working out the final mounting method for the three old style interface cards, hosting the 36 inbound signals from the 1131, plus my new driver board.
It was time for a power-on test of the box, with the FPGA hooked up and linked to the PC. I was expecting to see the 1130 working normally, without interrupts being triggered, and to see the appropriate state of the inputs reflected on the PC program. The drivers were not triggering spurious interrupt levels, which is a big step forward, but I still need to methodically work through tests to ensure all signals are working properly
Frankly, during the time a couple of days ago when I did the validation tests of the need for a pullup to SLT +3V, I lost my labeling on two of the four interrupt level wires and between the cycle steal request and channel write gate wires. Thus, I will need to determine them experimentally and modify, if necessary, my programming of the FPGA and documentation of the signal assignments to boards, circuits, and connectors.
My first tests showed a flaw in how I had wxPython render the value of the B register, but in my initial diagnostics of the PC side program I could see it was a rendering problem. Too, I found some apparent slight wiring swaps of a few signals, such as the T clock times. It was important to get to the bottom of these, thus I began monitoring all the signal values coming in from the 1131 with voltmeter (and oscilloscope as necessary).
I found that I physically wired the T clock signals in order from circuit 1 to 4 of the first board, thus any mixup in detecting which is active may be a problem in the wiring to the fpga, inside the fpga logic or in my PC side program. Upon investigation, it became obvious that the connector from the flat ribbon cable to the fpga flipped rows A and B, thus scrambling all the signal assignments I was using.
I am laboriously working through the FPGA logic to compensate, but also updating all the documentation as otherwise it will be very very confusing if I have to look at anything in the future. Another problem I found was that I had wired the driver circuits using a pair of pins on the FPGA which are a constant 3.3V (logic level 1).
I reassigned some lines and rewired the two signals that had been misconnected to C18 and D18, hooking them up to C15 and D15 instead. It took quite a few hours to straighten everything out.
The signal OSC Phase A runs continually, whereas I assumed it was the gated phase A signal that drives all the logic. That latter signal would not change state when in single cycle or stopped mode, and would jump high when the Start key is depressed in SS mode and jump to low when the Start key is released in that same mode.
I don't see the DC Reset signal coming through when I push the reset button on the 1131 console - needs a bit more investigation. Otherwise most signals are coming in just fine. I did spot one wire on a receiver board that was not well soldered and corrected it.
I feel I should continue testing in this mode, signal by signal, until I have high confidence in the signal transit between 1131, my interface box and the PC. Making good progress debugging and proving out the signal integrity.
It is definitely working better, although I still have a few small mixups to resolve. The daylight ran out and I had to close up the garage, looking forward to further improvements tomorrow.
It was time for a power-on test of the box, with the FPGA hooked up and linked to the PC. I was expecting to see the 1130 working normally, without interrupts being triggered, and to see the appropriate state of the inputs reflected on the PC program. The drivers were not triggering spurious interrupt levels, which is a big step forward, but I still need to methodically work through tests to ensure all signals are working properly
Frankly, during the time a couple of days ago when I did the validation tests of the need for a pullup to SLT +3V, I lost my labeling on two of the four interrupt level wires and between the cycle steal request and channel write gate wires. Thus, I will need to determine them experimentally and modify, if necessary, my programming of the FPGA and documentation of the signal assignments to boards, circuits, and connectors.
My first tests showed a flaw in how I had wxPython render the value of the B register, but in my initial diagnostics of the PC side program I could see it was a rendering problem. Too, I found some apparent slight wiring swaps of a few signals, such as the T clock times. It was important to get to the bottom of these, thus I began monitoring all the signal values coming in from the 1131 with voltmeter (and oscilloscope as necessary).
I found that I physically wired the T clock signals in order from circuit 1 to 4 of the first board, thus any mixup in detecting which is active may be a problem in the wiring to the fpga, inside the fpga logic or in my PC side program. Upon investigation, it became obvious that the connector from the flat ribbon cable to the fpga flipped rows A and B, thus scrambling all the signal assignments I was using.
I am laboriously working through the FPGA logic to compensate, but also updating all the documentation as otherwise it will be very very confusing if I have to look at anything in the future. Another problem I found was that I had wired the driver circuits using a pair of pins on the FPGA which are a constant 3.3V (logic level 1).
I reassigned some lines and rewired the two signals that had been misconnected to C18 and D18, hooking them up to C15 and D15 instead. It took quite a few hours to straighten everything out.
The signal OSC Phase A runs continually, whereas I assumed it was the gated phase A signal that drives all the logic. That latter signal would not change state when in single cycle or stopped mode, and would jump high when the Start key is depressed in SS mode and jump to low when the Start key is released in that same mode.
I don't see the DC Reset signal coming through when I push the reset button on the 1131 console - needs a bit more investigation. Otherwise most signals are coming in just fine. I did spot one wire on a receiver board that was not well soldered and corrected it.
I feel I should continue testing in this mode, signal by signal, until I have high confidence in the signal transit between 1131, my interface box and the PC. Making good progress debugging and proving out the signal integrity.
It is definitely working better, although I still have a few small mixups to resolve. The daylight ran out and I had to close up the garage, looking forward to further improvements tomorrow.
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