Sunday, August 9, 2015

Adding CRC to the fast SPI link capability of the SAC Interface Box


I made another try to run the DCIP utility on the 1130 today, after loading the file from my PC into memory via the SAC Interface Box, but it still looped. I did notice that the 1442 reader is in a funny state, which might be causing problems with the program.

The reader didn't put on the power lamp until I pushed the NPRO button, then I could hear a hum from the motor spinning. Since I have the belts removed, having taken out the punch mechanism, the reader isn't really in good shape to run. I will remove the cables from the 1131 to the 1442 for the time being.

I decided to bolster the reliability of the high speed link I will use between the main (ztex) fpga and secondary fpga or microcontroller boards to provide more fanout of signal lines. I need the data exchanged to be extremely reliable as a flipped bit might trigger some FSM shift or affect the mechanical motion of a peripheral.

The current logic is a SECDED (single error correcting, double error detecting) hamming code that carries 120 bits of data with 8 bits of parity to allow some self-correcting, but some multiple bit errors can slip through.

I decided to take 16 bits of the 120 bit payload space for a cyclical redundancy check (CRC) which is generated on the remaining 104 bits of payload, after which the data plus CRC is encoded with the hamming coding.

The idea is that the hamming code can correct the infrequent single bit errors, but then the CRC validates that the presumably recovered/validated data pack passes muster. This will let me push the technology in terms of distance and bit rate without having to spend too much on extreme link technology.

I found a great website ( which creates VHDL or Verilog for parallel CRC logic - pretty much any width and polynomial, emitting code that is free to use as long as you retain the copyright notice. I spent the evening finishing up the CRC generation and checking logic inside the SAC Interface box, using the parallel CRC logic I just included.

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