Testing virtual 1442 card reader/punch functionality
My final test last night had failed to complete the read cycle - which I had modified to resolve a race hazard I detected in the time when I was changing the card column number and thus the driven bits into the 1130 core would change. First task is to look over that code, find and correct the problem as well as set up diagnostics in case I didn't resolve it on the first try.
I spotted the flaw immediately when I looked at the VHDL, so back to testing as I intended to last night. I ran in single instruction mode to watch what happened. My read cycle FSM should be interlocked to require the XIO Read instruction to occur for each of the 80 card columns, but when I issued the first read, the FSM ran through all 80 columns.
Corrections made, it was back out to the machine to run the final testing for the morning. Running in SMC mode gets the columns lined up correctly in memory, but running in full speed produces these flaws:
- The off by one error in memory contents versus card contents, again
- Not seeing any non-zero values in the prepunch buffer when I fetch it after two cards are read, yet the second pass through the virtual card routine should have copied the pre-read buffer over to the pre-punch buffer.
- Python fetches the pre-punch buffer twice, apparently seeing the XIO IR twice (again).
When I am back from time out with my valentine, I will dig into this some more. By late afternoon, I was able to look at the system again. I made some adjustments but wasn't certain that I had it fixed - definitely need to do testing. I changed the diagnostic LEDs to look at the pre-punch buffer contents rather than the pre-read buffer. This way I will know if the copy-over from pre-read to pre-punch took place correctly.
If the data copies over but is fetched as zeroes, my problem is in the transaction that fetches the buffer contents. If the buffer is not copied over, the problem is instead in my copy process. The test suggests that the data is correctly copied over but somehow not picked up correctly by the fetch transaction.
The good news is that the off-by-one error is gone - the card images are correct in core memory. Also, the double XIO IR problem has been eliminated. As a card reader, the virtual 1442 is just about ready to use. A touch more testing and I could consider it ready for prime time.
I still have to check the behavior when a card file is used up, making an empty hopper, with or without the 'last card' checkbox being selected. Without the last card checkbox, the virtual 1442 should become not ready, waiting for a new file to be opened which places new cards in the hopper. If the last card checkbox is selected, then the DSW that is returned after the last card is read will have the 'last card' bit set.
My remaining testing will focus on the rest of the feed process - fetch the result of the pre-punch buffer, then copy pre-read buffer to pre-punch buffer. When that is working, I can test that the punch function will update the pre-punch buffer properly. One final test of the stacker select operation rounds out my testing plan.
A good day of progress on the virtual 1442 device adapter and a pleasant way to close out the evening.
Implementing physical plotter (1627 equivalent)
I switched over to the Digilent Nexys2 board and began by assigning pins to the 1627, 1134 and 1055 devices. I then routed them to the appropriate bits of the 104 input and 104 output bits carried over the fast link between this slave fpga board and the central ztex board. Once this is ready, I can begin wiring the plotter into the Nexys2 and conducting some tests of my adapter logic.
Implementing physical paper tape reader/punch (1134 and 1055 equivalents)
I set up the pins and routing for the paper tape read (1134) and paper tape punch (1055) devices which I will drive from the Nexys2 board remotely. The 18 signals needed for the paper tape devices were assigned out of my 104 input and 104 output signals over the fast link.