Debugging 1442 function
Did a few rounds of different diagnostic signals, still not seeing the defect but it can't hide forever. When I found a set of signals that showed me I did one pass through the logic to load the pre-read buffer, but the overall index never got up to 78 or 79, I suspected I was somehow ending the transaction wrong or not properly picking up the new column starting number on subsequent passes.
I spotted a race hazard, a place where a confluence of bad timing could cause me to skip some or most of the write transactions. I closed up the opening but also stuck in additional diagnostics to more firmly establish what is happening.
The next round of tests did not work any better nor did I see any indication of what went wrong. Time to break up the push on the Python side so that I can see that state of the mechanisms at the right snapshots. With that information, I noticed a spot that was resetting my index to the starting column for all 10 values in a transaction.
I am now moving on to debugging how the XIO read will populate the pre-read buffer locations as the virtual card reader issues 80 interrupts and the program responds 80 times with an XIO Read and then a reset of the interrupt level. At the end of 80 interrupts on level 0, we get an interrupt on level 4 which informs the program that our card is complete.
Moving forward nicely. The FSM completes the push of the card image, triggers the read cycle to issue 80 interrupts on IL0 which should trigger 80 XIO Reads and BOSCs from the program. I found a timing issue with when I triggered IL0 that forced a rapid loop.
The FSM also moved forward to trigger a dummy XIO Init Read, which my Python code uses to begin fetching the pre-punch buffer up from the FPGA. If this had completed by requesting all 80 columns, the FSM would then have copied the pre-read buffer into the pre-punch buffer and triggered the operation complete interrupt on IL4.
I put in some diagnostics to show me that I do seem to be correctly loading the pre-read buffer, since I displayed the first column top 8 rows on my GUI and they matched what I first sent - a good sign. However, the read emitter function is not working properly yet.
I did some minor cleanup and improved the instrumentation, then did a last round of tests tonight. The main FSM jumps ahead to send the faked XIO IR to the Python program but the 80 column card reading has not yet finished. Perhaps because of the skip ahead, the FPGA and Python get out of sync and I see timeouts. I think it is that the routine to fetch the pre-punch buffer is not working correctly and stalls.