Fixing design flaw in mirror 1442 mode, plus other things

The engine is humming along and the oil leak is gone, now that I finished up the replacement of the valve cover and cam chain tensioner gaskets. Pretty easy if the tool isn't fake junk like the first one. Putting the car in with the shop to have the timing belt replaced and do other work that is more elaborate.

Off to help a buddy move collectibles from a house he is selling in Morro Bay and into a nearby storage facility - I will be tied up until next Monday. Considering working on the Python program GUI when I am back in my hotel room each night.

SAC INTERFACE FOR ADDING PERIPHERALS TO THE 1130

Implementing mirror 1442 reader/punch

In a quick review, I noticed that I have used the low bit of the command 6 for two purposes - not ready status and mirror adapter mode. I needed to reassign the bit used to switch between mirror and virtual adapter modes. I chose to use bit 0 to set to mirror mode and bit 1 to set to virtual mode. The other bits I am sensitive to in this transaction are bit 15 (not ready) and bit 3 (end of file).

All the logic is updated in both fpga and PC program, but the only testing I can do, while my 1442 is offline, is to verify that virtual 1442 mode still works correctly.