Monday, May 29, 2017

Good progress on the disk tool debugging


I set up a simulation testbench to closely examine the serializer, a module which loads parallel 16 bit Alto data words and shifts them out one bit at a time upon request from other logic in the disk tool. Symptomatically, I am seeing nothing but '0' bits shift out of the serializer and it never raises the signal asking for the next 16 bit word to be set up for loading. 

Most of my logic wasn't being executed. I stared for a while then saw it. My first test in the process checks to see if we are at startup, when an input signal is '1', to set up initial conditions. Once that goes to '0' it checks for the request to send the next bit and does its thing.

However, I coded the first test this way:
if loadword <= '1' then
The sequence <= means assignment, not a test for equality! The line actually forced the reset input signal to be on and always passed that first test. It never got to my other logic to serialize and emit output.  It should have read if loadword = '1' then

With that moronic error fixed, the serializer began to work. I could move back from simulation to the real testbed and see that I was now emitting the signals that I should. I could zoom back out and watch the actual written stream to verify that it wrote the preamble, sync word, two header data words, checksum, postamble, etc.

I found the system emitting the preamble of zeroes, the sync word and first two data words, but the checksum being emitted was incorrect. Further, once it wrote the postamble the clock shut down and the remaining two records were not attempted.

It is time to hook up the logic analyzer and record what occurs during the writing of the first field. I will also capture the running checksum since the first problem I saw was an incorrect checksum being written. 

The watchdog logic shut down the write sector operation before the first record was complete - clearly wrong behavior. I temporarily turned off the watchdog logic and was able to write the entire sector on the testbed.

The overall pattern and data content appears good, at least up to the first data word of the label (second) record in the sector. I looked at the signal which is output by the serializer each time it is ready for the next word to be loaded and the count between the sync bit of the two records was indeed 14 word times, just what it should be.

The sync words are correct, the two header record data words are correct, the postamble of that record and the preamble of the label record is correct, the sync word for the second record and its first data word match exactly.

However, two things are not perfect yet. First, and most seriously, the checksum being written out is not correct. Second, the length of time between words is a bit too long, so that the fourteen word times I wrote out take over 158 us to produce when the expected duration is closer to 135. An 18% elongation of each bit cell would produce this timing.

I will be simulating the bit cell timing machinery tomorrow to either fix it or determine that I have a problem in the oscillator on the FPGA board. If the fpga board runs a bit slow, at 4.24MHz instead of 5 MHz, it would create this behavior.

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