Thursday, September 7, 2017

Making progress on the disk emulator role and its interface board


I hooked up power and began testing the functionality of the disk emulator interface board. I first applied +5 and 0 to the signals that are inputs from the Alto to the emulator - verifying that each FPGA input pin swung to +3.3 and to 0 based on that applied voltage. So far so good - my FPGA logic will detect the signals sent by the Alto to the 'disk drive'.

Next, I put a voltmeter on the pins that will deliver signals to the Alto based on the output voltages from the FPGA. I applied +3.3V and 0V to the fpga pins and looked at the resulting outputs to the Alto.

Only two signals every moved off zero - the ReadData and ReadClock signals that were terminated with the resistor networks on my board. That highlighted the fact that my bus driver chips that produce the outputs are open collector gates. That means they will conduct to pull a line down to ground but they do not produce +5V when off.

I had just removed all the resistor networks for these output gates from the board, since the Diablo terminator had no resistor nets. However, the Diablo drive had gates which produced 5 or 0V, not open collector gates.

Now, I have to hook up pull up resistors to all those output signals that are not working now. I won't install the pulldowns to ground, thus no terminator for signal reflections, but the pullup will ensure that I generate appropriate TTL output voltages.

I will figure out a reasonable resistor value for the pullup, one that keeps the current in the open collector gates below their limit, but otherwise can deliver the highest voltage when the gate is not firing even through the load resistance of the Alto input gates. 

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