Monday, October 15, 2018

Looking at the AGC Block II core rope memory structure


Rope memory

The read only memory (called fixed memory in the AGC) was constructed of core rope. This is a technology that is actually different from the read/write core memory that most know. For one, it does NOT use small ferrite cores nor does it depend on cores retaining the state of the stored bit.

The cores used in rope memory are larger steel bobbins wound with a thin magnetic tape. These are large enough to allow many wires to be threaded through the center of the bobbin. Data is stored by the simple process of threading a wire, for a 1 bit, or bypassing the core to reflect a 0 value.

The process of reading the core rope contents is similar to regular core memory, but not the same. To read a particular bit, select lines are chosen to magnetize the bobbin. First, the bobbin is set by a current in one direction, then the current is reversed causing the magnetic flux in the bobbin to flip.

Any and all sense wires threaded through the bobbin will have a pulse generated as the bobbin flux flips. The sense amp reads this as a 1 value. If a sense wire for a bit is not threaded through the bobbin, it does not see a pulse thus the amp records it as a 0 value.

Since a core rope module for the block II AGC supports 6K words of 16 bit memory, there are quite a few bits involved - 98,304 in all. At one extreme, you could build a huge bobbin that allows up to 98,304 sense wires to fit through the center. Then, regardless of the word address, you set and reset the one bobbin to generate all the values on the wires. Switching the many sense wires is the main complication and requires a lot of circuitry.

At another extreme, you could provide one bobbin per every bit, installing 98,304 bobbins and obviously requiring a very large volume to hold them all. There is no space advantage to this method over regular read/write core.

Where core rope shines is in its ability to put more than one bit in a bobbin, unlike regular read/write memories that use one core per bit. This gives it quite a volume advantage over the same amount of regular core memory.

The particular tradeoff between sense amplifiers, bobbins and number of wires through a bobbin center that was chosen by the MIT designers for the final core rope module is to install 512 bobbins in a module. Two modules together make up a rope, although they are not combined in any way to form a single logical rope.

To select a particular word, we divide up the address range to select one of the 512 bobbins - 9 bits are used for this. We then select which of 12 strands of the sense wires are tested - another 4 bits for this, generating 6,144 unique total locations when combined with the bobbin.

A module selector takes 1 bit, picking which of the two 6K modules are desired. The choice of which of the three logical ropes, units of 12K words, takes another 2 bits Thus, 16 bits of address information pick out a word.

This addressing could range up to 64K but only 36K is physically implemented. 1/4 of the address range for strands is unused (12 strands selected by a 4 bit address), and 1/4 of the rope count is unused (3 ropes selected by a 2 bit address).

The machine architecture only has 12 bits for addresses and by definition, if the top two bits of the address start with 00 then the data is in the erasable (read/write core memory) module. Thus, of the 4096 addresses that can be generated in an AGC instruction, 1K refer to the erasable and only 3K are left for the fixed (core rope).

The last 2K of address range is directly assigned to two 1K blocks of rope, starting at octal 4000, but the second 1K range is switched to any of the 36K implemented in fixed memory based on the value in the register which holds the index of the 1K block.

This bank switching register only supports 5 bits for addressing, choosing among 32K blocks of fixed memory. To get to the remainder, the AGC implements yet another technique, a super-bank bit that switches the top end blocks. The super-bank bit is assigned in channel 7.

When the value in the FBank register is 0 to 23, it selects banks 0 to 23 without regard to the super-bank bit. However, when the FBank has 24 to 31 in it, the super-bank bit adds 8 to the number. That is, super-bank=0 then 26 in FBank selects bank 26. If super-bank=1, then 26 selects bank 34.

Physically, the AGC has six core rope modules installed, each supporting 6K words. The addressing logic for reading fixed memory has to select which rope, which module in a rope, which bobbin in a module, and which strand woven through the bobbins; This strand of 16 wires drives the 16 sense amplifiers to produce the output word.

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