Sunday, October 14, 2018

Looking at read/write core memory used in AGC Block II


Erasable Memory cycle and timing

The main oscillator is divided in half to produce a 1.024 MHz main clock which steps through a 12 stage ring that constitutes the memory cycle of the machine. The memories are based on magnetic cores, thus the process of reading also resets the core to zero and a second half of the cycle must write back the value to restore it into the memory - or a changed value to store into the location replacing the old value.

By the beginning of the sixth step of the ring, the contents of a memory location, either the erasable or fixed memory, is available on the bus for use. By the beginning of the 9th step, a value in the register is latched to be written out to the same memory address if it was in erasable memory.

The erasable memory consisted of lithium ferrite core stacks, manufactured by either EMI or RCA. Addressing of the memory makes use of bits 0 to 11 of the instruction word. If bits 11 and 10 are both zero, this indicates that we are accessing the erasable memory.

The memory scheme of the AGC is complicated. The 2K of memory is implemented as 8 banks of 256 words. When address bit 9 and 8 are both 1, we are referring to a bank indirectly, depending on the contents of the BBank register to select which of eight banks to use. When the high two bits are not both on, then we are directly addressing banks 0, 1 or 2 depending on the value of bits 8 and 9.

This means that from the CPU standpoint, we have only 1K addresses to select. Addresses from 0 to 767 are directly hooked to the first three banks of the physical core plane, while addresses from 768 to 1023 are hooked to one of the eight banks based on the contents of the BBank register

Physically, the core stack is a sandwich of 128 planes, each having an array of 16 x 16 cores, all folded tightly in a small space. We can look at each logical bit plane independently to understand addressing, thus we have only 8 small planes to consider,

The eight total small core planes can be thought of as an array of four across and two down. In the Y X signals run vertically through two small core planes. Y signals run horizontally through four small core planes. They intersect in only one plane.

 The address bits 0, 1 and 2 are used to select one group of eight cores out of eight such groups in the X selection lines. Two groups of eight fit on each of the small core planes, thus we have four planes across in the X direction.

Address bits 3, 4 and 5 will select one of eight of the cores in the group  thus the combination of all six bits selects one of the 64 X rows of cores. This activates an X row in both of two small core planes, which will be distinguished by the Y selection line that activates in only one of the two selected planes.

Address bits 6 and 7 select one of four groups of 8 lines in the Y direction. Bank selection logic picks one of the eight lines in a group, thus one of the banks of 256 words. Selecting 64 X and 4 Y lines with the regular address bits 1 to 7 picks which of the 256 works you want in a bank. The 4 Y lines each represent 8 physical lines, the other end of which is determined by the bank select to finalize on one of the 32 physical Y lines in the array.

There are eight banks, picked by the bank selection logic using bits 8 and 9. This works in a special way. If bits 8 and 9 are 00, 01 or 10, this selects the first three banks. If bits 8 and 9 are 11, it looks at the BBank register and uses that value to select which of the eight banks to use.

Inhibit drives run through each core in each plane, so that we can inhibit the setting of each plane individually. A sense wire runs through each core in each plane and allows detection of the case where a core is reset to 0 but was previously magnetized as a 1.

The memory stack is folded to fit best in a rectangular solid shape, its steering diodes are put on top and the entire contents are encapsulated in a wide module (B12) that will plug into tray B.

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