Finalizing and simulating the Diablo disk archiver tool design

DIABLO DRIVE TO BE USED TO READ AND ARCHIVE MY 2315 CARTRIDGES

I have a substantial library of 2315 disk cartridges that I acquired, mostly as part of the purchase of my own 1130 system. I also have a Diablo Model 31 disk drive with the rare standard density heads that match the bit rate of the internal (13SD) IBM disk drive in the 1130 system. I intend to use the Diablo to read and upload all the disk images, avoiding risk to my own internal disk drive if any of the cartridges have a flaw I don't detect that causes a crash. 

ARCHIVER BEING WHIPPED TOGETHER WITH ARTY A7 FPGA BOARD

I had a Digilent Arty A7 FPGA board on hand and chose it to support this role. It has enough onboard DDR3 RAM to read in and hold an entire 2315 cartridge, 1,013,376 bytes and enough logic blocks to implement the fairly simple logic needed to sequentially read all 1,624 sectors of 321 16-bit words, beginning at the home track and stepping forward one track at a time to the last of the 203 cylinders. 

It will then upload the image over a USB serial link where I can post-process the contents into an IBM 1130 simulator format file and then into a Virtual 2315 Cartridge Facility file that can be accessed on a physical 1130. I am leveraging code to format the data into ASCII and send it out over serial that was developed by William Carter at Eclektek LLC.

GOOD SIMULATION VERY IMPORTANT FOR DEBUGGING FPGA DESIGNS

It is important to carefully model the signals, especially their relative timings, to see that the state machines and other logic performs as intended. I work to introduce timing variations, worst case situations and anything else I can think of that could reasonably happen to the FPGA when actually driving the Diablo. 

SIMULATION VERIFICATION PROGRESS

The Diablo Archiver consists of a number of modules that perform various functions. As of now, these are:

• clock_and_reset which generates the asynchronous reset to initialize state machines
• seek_to_cylinder which performs a one track move inward
• sector_and_index which tracks the upcoming sector and indicates arrival
• bus_disk_read which reads the sector, checks for errors and pushes data to RAM
• archiver which steps through all sectors and asks for them to be read
• uploader which sequentially fetches the sectors from RAM, formats and sends them over serial
• dram_controller which takes the requests from above and controls the DDR3 RAM
• YASUTX and UART_DEBUGGER2 for the serial output

I have finished fully testing the bus_disk_read, seek_to_cylinder, sector_and_index, clock_and_reset and archiver modules. Next up I will simulate the dram_controller and its RAM functioning, then the uploader module with its serial stream output. The final simulation will pull the entire FPGA design together. 

EXAMPLE OF SIMULATION OUTPUT

Here is a simplified excerpt of the simulation of the archiver module to show the successful behavior of the machine as it reads the last sector of the cartridge - cylinder 202, head 1, sector 3.