Simulation challenges since Vivado not correctly simulating its IP components

NEXT UP WAS THE DRAM CONTROLLER LOGIC FOR SIMULATION AND VERIFICATION

This module will drive the memory interface IP (intellectual property) that Xilinx provides for their FPGA devices. It uses the cylinder, head, sector and word number data to generate a RAM address and is triggered by a signal to write a given word to RAM, or later on by a signal to read back a given word.

CLOCK WIZARD FOULED UP IN SIMULATION

The first surprise was finding that the Clocking Wizard was not simulating correctly. The FPGA board operates with a 100MHz clock but the memory interface needs a 200 MHz and a 167MHz clock to function properly. The IP will take the board's oscillator and use it to generate 200, 167 and 100 MHz clocks for use throughout my design. 

Under simulation, the outputs were 100, 83.4 and 50 MHz while the input I produced in the testbench was correct at 100MHz. Regardless of what rate I produced for the input signal - 50, 100, 200 or anything else - the outputs were always 100, 83.4 and 50. Lots of experimentation but I never did get the proper clocks while simulating. I did build a simple design using the same clock wizard that I loaded into the board so that I could use my oscilloscope to observe the frequencies produced in real operation.

MEMORY INTERFACE ALSO MISBEHAVES IN SIMULATION 

The second IP to be seen working improperly was the generated memory interface for the DDR3 RAM chip on the board. It never generated the chip reset signal to the physical RAM chip, nor did it properly reset or come out of reset based on the actual reset signal I generated in the test bench. At first I ascribed this to the incorrect clock speeds, but a special version of the clock IP set to 400, 334 and 200 gave the the designed 200, 167 and 100 yet did nothing to alter the behavior of the memory IP. 

NOT YET ABLE TO CHECK BUT SUSPECT THE FIFO IP WILL ALSO FAIL TO WORK

Until the memory interface completes calibration and comes ready, my design isn't ready to push words into the FIFO for writing nor to trigger reads and push results into the read FIFO. These are necessary because the memory interface IP produces a user interface clock at 83.4 MHz that must be used to interact with the IP, while my user logic runs at 100MHz. The FIFOs deal with crossing the clock domains.