Simulating my dram controller logic but not using Xilinx memory controller nor clock wizard

CLOCK WIZARD SIMULATION USING MY OWN CODE IS WORKING WELL

My own logic temporarily replaces the Clock Wizard IP that will run on real hardware, since the Vivado tool won't properly simulate the clocks. My code is emitting the 200, 167 and 100 MHz clocks properly.

MEMORY INTERFACE IP ALSO NOT SIMULATING PROPERLY, REPLACED

I wrote my own replacement for the memory interface to simulate the results my logic will be seeing when using the real IP on hardware. This is a very complex function but I can collapse the requirements down to the types of uses my logic makes, thus eliminating all the simulation of behaviors like calibration and periodic refresh cycles. 

This was still a bit of work to get the code to match the Memory Interface Generator IP documentation and to accept the way my design requests writes and reads. The MIG supports multiple ways to write data, for example - you can push the data before you request the write, simultaneous with the write request signals, or up to two clock cycles later than the write request signals. Fortunately, my design has picked just one of them so I only had to model that particular pattern.

VERY HAPPY THAT THE FIFO IP IS SIMULATING CORRECTLY

There are two First In, First Out (FIFO) queues I use to move data between the 100MHz clock domain of my general logic and the 83 MHz clock domain of the memory interface. The IP from Xilinx is simulated well enough that I do not have to replace that in the same way I had to replace the Memory Interface and Clock Wizard functions. 

WORKING THROUGH THE DRAM CONTROLLER MODULE SIMULATION NOW

My simulation test bench is driving various write and read requests, just as the archiver will request writes and the uploader will request reads. I am carefully inspecting all the signals and results to satisfy myself that this appears to work as intended. 

Once that is done, I will attempt a grand simulation of everything as it would be wired to the Diablo disk drive, merging the test bench code used in all my module by module simulations and producing a realistic set of driving signals and responses that should let me prove out my design as well as I can before hooking it up to the real disk drive.