Continuing testing of the 1130 MRAM board

REWORK DONE TO THE BOARD AND REINSTALLATION ON THE 1130 FOR FIRST TESTS

I lifted pins, added jumpers and wires, to resolve the design flaw I had discovered. The repaired board was put back on the IBM 1130. I then did some Load and Display tests with the logic analyzer connected to validate the behavior for these simple cases. 

It was still producing spurious sense bit outputs. I switched to the oscilloscope for an analog view of the signals. The spec sheet for the SN74LVC1G123 timer chip indicates that a logic low is 0.8V or lower and logic high must be 2V or higher. The unasserted state of the +Storage Read signal is around .2V and it sits around 3V when active. 

However, I can still see retriggering of the timer. The yellow trace is the +Storage Read signal, the green signal is the first time which delays about 800ns and the purple signal is the second timer which produces an 100-120ns pulse. The pulse is what generates the -Sense Bit X outputs. 

I can see the first timer immediately retrigger around the middle of the trace, thus the second timer produces more than one pulse. There is some funniness on the +Storage Read signal right as the second timer fires, which dips down low enough to look like a logic low. Thus as it recovers, the first timer fires anew. 

As a clue, when the word being read is all zeroes, the pattern above occurs. Just two pulses (one more than desired). However, when the word is mostly ones, the retriggering seems to continue long after +Storage Read goes back to low. 

I have to mull over how this might be occurring. I did fix the vulnerability where a machine cycle shouldn't send out sense pulses because +Storage Use is low. Whatever is happening here is not that condition. 

This may be an issue with inadequate ground conductance causing some bounce in the levels when many gates are switching, or perhaps I need to bump up the capacitor at the output of the 3.3V voltage regulator.