IBM 1130 MRAM memory board - root cause of the unwanted stream of pulses from the board being corrected

REALIZED THE CAUSE

I had made a tweak which I thought optimized my design, so that the timer pulses that control emitting the sense output bits are triggered by the rising edge of the +Storage Read signal. On the surface that seemed logical, as we only want to fire them off when we are doing the read portion of a storage cycle.

However, the genesis of the +Storage Read signal is when the IBM 1130 is in clock states T4, T5, T6 or T7. This happens on every machine cycle, not just during memory access. Thus, we would trigger the pulse to emit sense bits on the second half of every machine cycle, not just the ones we want. 

The +Storage Use signal is what indicates that a particular machine cycle involves a memory read. Thus, I should have triggered this when both +Storage Read and +Storage Use go high. Originally the design did use this logic, but to save gates I switched to simply using +Storage Read, forgetting that this is not just raised during a read attempt. 

RESOLUTION OPTIONS

There is one spare gate on a 74HC00 chip, a NAND, that I could press into service to make a signal when both +Storage Read and +Storage Use are high. The original design used this gate plus another that inverted the output to produce a positive going pulse as the trigger to the timer chip's notCLR input. I needed another gate for a different change so I made the ill fated decision to drop the +Storage Use from the trigger conditions. 

The solution is to use the spare gate on U14 to produce a low output when both +Storage Read and +Storage Use are high. The timer has three control inputs - ~A, B and ~CLR - which have to be reconnected. There are three ways the timer can be triggered - 

1. a rising edge on ~CLR while ~A and B are L and H
2. a rising edge on B while ~CLR and ~A are H and L
3. a falling edge on ~A while B and ~CLR are H and H

 The original design used option 1 but I only have a falling edge from the added NAND gate, so I have to shift to option 3. Thus those three control pins have to be rewired (actually only ~A and ~CLR but for technical reasons I change all three. 

Of course I could redo the board, waiting a couple of weeks for parts and the new PCB, but that is punishing. I instead looked for ways I could rework the existing board to function as intended. I did figure out a way to rework the board. 

It involves lifting six pins total from two chips to disconnect them from the existing board traces. Mainly this is due to traces running underneath the chip not just off to the sides, so that cutting traces would be more of a challenge. I then add some jumper wires across pins and over to the +Storage Read pin (cable T3 pin lower 6). 

REWORK STEPS

I have to lift pins 5, 12 and 13 from chip U14 (the quad NAND device) and pins 1, 2 and 3 from chip U5, the timer device. This isolates the pins from the existing connections on the board traces they had been soldered to. 

I then put short jumper wires between U14 pins 1 and 13, as well as 5 and 14. I then add a wire from U14 pin 11 (output of our NAND gate) to U5 pin 1.  On chip U5 I add short jumper wires from pin 8 to pins 2 and 3. Lastly, I run a wire from U14 pin 12 and the connector for cable T3, on the lower position 6 (+Storage Read). 

The schematic version of the rework is to disconnect the +3.3V connections to chip U14 pins 12 and 13, the previously unused gate. Wires run from these pins to cable T3 lower 6 (+Storage Read) and to U14 pin 1 where the +Storage Use signal is connected. 

Over at the existing connections to chip U5, we disconnect the three existing control signal connections.

Jumpers tie pins 2 and 3 to +3.3V while we run a wire from U5 pin 1 over to U14 pin 11 where our new control signal is generated. 

GOOD VERSION OF SCHEMATIC AND PCB LAYOUT