IBM 1130 MRAM memory replacement - investigating Parity Check and random data occurrences

LOGIC ANALYZER CAPTURE RESULTS

I hooked up the DSLogic analyzer to the 1130 to capture key signals allowing me to figure out what is going wrong with the read and write process and the phantom parity check issues. The device can sample up to 16 lines at a time, which is not enough for a full capture of every signal of interest, but should allow me to watch subsets until I spot an issue that hints at where to zoom in. 

If I had unlimited channels, I would capture:

• all 16 B reg values. 
• all 16 sense bit outputs
• check bit 1 and 2 sense outputs
• storage read and storage write commands
• T0 to T7 clock pulses of the 1130
• parity check detection signal
• all 13 SAR values going into the board

I began with sampling  some timing related information to see if I am doing things at the wrong time. I grabbed storage read, storage write, T0, T2, T4, T6, the parity check signal and some sense bit outputs including the check bits. If the sense bits are being produced at the wrong times, e.g. too late in the read cycle when we are already starting the write, then it might lead to the conditions I am observing. 

Doing a read of a word that is all zeros produces the correct data without a parity check, but when the word has bits that are a one, I saw that the board then was emitting a continuing stream of bits long after the read was completed. 

FAILURE MECHANISM

The circuitry for the B register will set the bit to one if a pulse arrives on the sense bit lines - any time that it arrives. It is not gated to only activate during the time of a read, it will flip on the bit whenever it arrives. Thus if my board emits sense pulses it is going to stomp on the B register. 

Why this is happening was not immediately obvious. I put a timer chip on a breadboard and tried to cause it to fire off a stream of pulses but couldn't create a plausible sequence to make this happen. The chip I am using on the board, sn74lvc1g123, is a retriggerable timer, thus it can produce a stream of repeating pulses in the correct circumstances. 

I will have to do some analog investigation, as the issue might be noise, invalid logic levels or other issues that won't show up on the logic analyzer.