Testing my new seek logic for the Virtual 2315 Cartridge Facility - 15

FPGA IN V2315CF UPDATED TO WORK WITH ELECTRONIC SWITCH VERSION

The FPGA inside the main box of the Virtual 2315 Cartridge Facility (V2315CF) was loaded with the updated logic that renders the output drivers of the box inert for signals that are directly connected in real mode between the 1130 and the 2310. This resolved a problem seen in the last test session, where I two sources were driving signals in opposite directions. I also added in the version of the seek shadowing logic that was hoped would be impervious to glitches. The terminator resistors were installed only on the signals that require them. 

TESTING WITH HAND ENTERED ACCESS PROGRAM

I ran the hand entered code that will repeatedly drive the arm between cylinder 0 and cylinder 200 as long as the 1130 is in run mode. The disk performed exactly as requested, stopping each time at 0 or 200, but the V2315CF got out of sync a bit. It recorded the lowest cylinder location as 2 and the top location as 202. Once it was out of position, it never locked in to cylinder 0. 

OBSERVATIONS OF SHADOWING IN THE V2315CF AS THE ARM MOVES

The logic in the V2315CF can observe the microswitch that turns on the -Home signal to logic low when the arm is at cylinder 0. Based on that, I can reset the current cylinder to 0 when we are beginning a seek when -Home is asserted low. That would have solved this particular issue, but if I had a program that zoomed back and forth between two cylinders that did not include 0 - say cylinder 10 and cylinder 190 - then if it got out of sync the microswitch fix won't help. 

DEVELOPED MODIFICATIONS TO SEEK SHADOWING LOGIC IN FPGA

I put in the logic to reset the cylinder whenever the arm is sitting at cylinder zero. I also made changes to hopefully address whatever issue caused it to get out of sync with the actual disk arm. When I get back to the shop I can test this to see if I resolved the vulnerability or not. I will also have the logic analyzer collecting data as I test this out, to see if I can spot any other situations that cause the FPGA logic to misbehave.