CAPTURE SET UP TO UNDERSTAND WHY WE ARE BUMPING ADDRESSES WEIRDLY
The observed symptom was that when I did an XIO Write command with a buffer filled with 321 words whose values were essentially the same as their word number, thus easily identifiable, the Virtual 2315 Cartridge Facility received the first 111 words of the buffer correctly but then had a strange pattern seemed to be captured for the rest of the sector. We jumped up to word 225 and then were sent every OTHER word in the buffer from that point, meaning the memory address the 1130 was using to fetch memory from the buffer was advancing by 2 instead of by 1.
The logic analyzer produced a spreadsheet that I analyzed with a quick Python program to find the clock transitions and capture the data bit values, assembling them into 1130 words and validating the error checking code bits. Below is the beginning of the capture, which matches the pattern I wrote into the memory buffer for the XIO Write instruction. It shows the relative timing in microseconds from the start of the write operation as well as the extracted word. It would flag any error checking violation to the right of the word.
Below is the area in the data capture where we see the jump in core memory addresses and the stride of memory addresses increasing to 2. We should be fetching 0x0071 next but instead grab 0x00E2 and then step by twos through the remaining words.
I realized after a long while that in fact the value I believed to be 0x00E2 was actually 0x0071, the bits apparently shifted left, with the ECC check passing because the word had four bits that were 1, so the ECC value would be 0000. I looked closely at the graphical logic analyzer trace and confirmed that I was seeing the data fetched correctly from memory but shifted a tad due to a glitch on the -Write Clock Phase B line.
The hardware that requests the memory fetching is designed with only one function - increment by 1 - which occurs at the end of the memory fetch of a word so that the address is bumped to the next position. In modern logic, this is a ripple counter.
I don't see any mechanism that would explain the big leap somewhere in the middle of correct operation nor the double stride used for the rest of the write. I put the logic analyzer on all the address bits coming from this ripple counter and saw it perform perfectly.
RESULTS OF THE DATA CAPTURE INSTEAD POINTED AT GLITCHES IN SECTOR MARK
What I saw in the traces, particularly the fact that the trailing words of the sector were all zero values, were the expected behavior if a write operation stops too early. The design of the 1130 keeps sending zero words until the actual end of the sector even if the word count for the write command has reached zero earlier. Assuming that bad addresses were fetching words from 1130 memory that all were coincidentally zero was a leap of faith, and unwarranted.
Looking at traces I captured, I found that -Write Gate was turned off at the 5 millisecond point instead of remaining on for the entire 10 ms duration of a sector. This turned my suspicion back to the physical sector mark pulse that was arriving around the point we stopped grabbing data from the 1130.
The drive produces eight 160 microsecond pulses spaced evenly around the perimeter of the disk platter, one each 5 ms given the 40 milliseconds it takes for the disk to spin once at its 1500 RPM nominal speed. IBM chose to divide the perimeter into four sectors rather than the eight defined by the hardware pulses. This allowed enough space on the logical sector to write 321 data words.
To accomplish this, the 1130 disk controller logic implements a simple divide by two circuit using a flipflop that is toggled by the physical -Sector Marker pulse coming from the disk. IBM's Solid Logic Technology (SLT) circuitry in the 1130 uses flipflops that are triggered by a falling edge of a signal.
They also produce a parasitic false output pulse if the set or reset input is pulsed when the flipflop is already in the requested state. IBM designs around this by adding gates in front of the set and the reset inputs that only allow a pulse if the flipflop is not already in that condition.
The gates in front of the flipflop are also edge triggered - IBM calls these AC triggered gates. When the trigger signal, marked with the letter N on the input of the gate symbol, has a falling edge, the gate produces a short negative going pulse on the output pin on the right of the gate symbol. However, it is only sensitive to the input falling edge if the other inputs, marked with a right triangle symbol, are at logic low (0V). If any other input is high, the gate ignores the falling edge on its trigger input and does nothing.
Thus, in the logic diagram excerpt below, when the trigger input goes low, the non-inverted output of the flipflop is connected to the gate in front of the flipflop set input. When the flipflop is on, the non-inverted output is high and that prevents the gate from sending a set pulse to the fliplop. When the flipflop is off, the non-inverted output is low and the gate can send a pulse to set the flipflop on.
However, the gate connected to the reset input of the flipflop is conditioned by the inverted output of the flipflop. If the flipflop is already set, the inverted output is low and that allows the gate to send a pulse to reset the flipfop. When the flipflop is not set, the inverted output is high and the gate blocks a reset pulse from being applied.
The -Sector Marker pulse from the disk drive sits at logic high except for 160 microseconds, once every 5 milliseconds while the disk is rotating. The inverter gate at the top left changes the signal so that it is low most of the time and goes high for 160 microseconds. When the 160 microseconds ends, the falling edge of that signal is passed to the two gates that drive the flipflop set and reset inputs. The action of the two gates means that it toggles the flipflop to its opposite state by routing a pulse to either the set or reset input depending on the current state of the flipflop.
Thus the flipflop goes on and off based on the end of the -Sector Marker pulse. The gate at the top right of the diagram is a simple combinatorial NAND gate. When the inverted -Sector Marker pulse, now high during the 160 uS interval, occurs while the flipflop was set, the 160 uS signal passes through as a negative going 160 uS pulse once every other sector marker. In essence, the top right gate blocks every other sector marker pulse.
In addition to the eight sector marker pulses that arrive as the disk platter rotates, there is one -Index Marker pulse of 160 uS per rotation that marks which sector is number 0 out of the four logical sectors that pass by the read/write heads during a spin. At the bottom, the -Index Marker pulse negative edge, when it begins its 160 microsecond duration, will force the flipflop to reset so that we are set up to block the next sector marker.
The index marker occurs just after one of the eight sector marker pulses, so that this position on the disk marks the start of a logical sector, blocking the next sector marker and passing the one 10 milliseconds later. This keeps the disk controller in sync with which sector is arriving next for when a read or write operation must start.
Astute readers might wonder at the risk of the parasitic output pulse since the index marker pulse might reset a flipflop that is already in the reset state. Indeed that blip might be emitted on the non-inverted output of the flipflop if it was already reset when the index marker arrives. That does cause the top right gate to have a short term high on one of its inputs, but this does align with when the sector marker pulse is active so nothing comes out of the final gate. The timing diagram below shows how this works out:
With this background, you can see how my next logic analyzer trace captured the cause of the short write duration. We were watching the signals involved in switching off a write operation, The important signals to look at are the -Write Gate, -Four Sector Pulses, +Sector Marker (the inverted output of -Eight Sector Pulse from the logic diagram above), +Alternate sector (non-inverting output of the flipflop), and -Alternate Sector (inverting output of the flipflop).
On the left of the trace, we have the first sector marker, the one that defines the start of the sector we are writing to. The inverted sector marker pulse goes high for 160 uS. The falling edge of -Sector Marker, rising on the inverted signal, turns on -Write Gate to begin the sector. The flipflop resets at the trailing edge of the inverted signal +Sector Marker which would block the next sector marker pulse from passing through to the output of the logic diagram as signal -Four Sector Pulse.
However, when that next sector marker pulse arrives, we get a glitch that appears as a short sector marker immediately followed by the normal sector marker. The falling edge of +sector marker causes the flipflop to be toggled, then the remainder of +Sector marker passes through as -Four sector pulse and turns off our write. We end prematurely because of the glitch - had the pulse not had the brief blip down, we would have blocked the -Sector Marker and not reacted.
The flipflop is reset at the start of the true sector, but sets briefly before resetting again when the second -Sector Marker ends. The signal line where I produce the -Sector Marker pulse is kind of unique, as it is generated by the V2315CF when in virtual mode, but we pass along the real disk drive pulses when we are running the real (hybrid) mode.
COMPLICATIONS OF REAL AND VIRTUAL MODE
Some signals between the disk drive and the 1130 disk controller logic are always coming from the V2315CF, such as the -Write Clock Phase B, while others may come from the disk drive OR the V2315CF depending on our mode of operation. The normal mode for the V2315CF is called real, where we spin up the internal 2310 disk drive inside the 1130 and let is generate signals such as sector mark, index mark, file ready, access ready (for seek operations moving the disk arm) and home cylinder. The V2315CF watches those signals and keeps track of what the real disk drive is doing. In virtual mode, we leave the 2310 switched off and simulate all the signals from inside the V2315CF.
Electrically, we bridge the signals from the disk drive to the 1130 controller logic using electronic analog switches on the 2310 Interface Board, a component of the V2315CF. When the switch is set to real mode, the analog switches are closed and they route the signal coming in from the 2310 to the wires going out to the 1130 disk controller. The FPGA logic in the V2315CF does not emit anything on those signal lines while in real mode; since the outputs are open collector gates, we emit a logic 1 to leave the output line undisturbed. The 2310 disk drive provides a pullup resistor to logic high (3V for SLT) and grounds the signal line to send a logic 0.
In virtual mode, the switches are disconnected and the signal is produced by sending logic 1 and 0 values to the open collector output gate. To provide a pullup because the 2310 is no longer operating, we depend on two things. The termination resistors on the V2315CF have both a pullup to +5V and a pulldown to ground, with the resistor values creating an impedance match to the ribbon cable and other wiring. They are set to give a logic high value of 3V at the signal line when our open collector driver is at logic 1 and pull down to ground when the driver is emittiing logic 0.
The challenge is how to handle pullup resistors and termination resistors for when we are in real mode, where these can interfere with the pullup resistors in the 2310 disk drive circuit. I changed these to a much higher set of values that will still set 3V when in virtual mode but have light impact on the levels produced by the 2310 circuit when we are in real mode.
Because the electronic switch is shorting the 2310 signal to the 1130 disk controller input, our terminators are mid stream and don't do much for real mode, but work adequately when in virtual mode. They have the downside that they don't match the impedance well in virtual mode, acting as a 6K ohm termination for a 100+ ohm line.
This can give us ringing and glitches, something plaguing the sector marker signal right now. When I had the sector marker terminator resistors at the correct impedance matching - 169 and 249 ohm values - the glitches showed up in the operation. That matched the traces I just showed.
When I pulled the terminator resistors off entirely, the write failed in a different way due to glitches.
Here the glitch occurs on the sector marker pulse at the start of the logical sector. There is a glitch on the falling edge of -Sector Marker (inverted -8 sector pulse is a rising edge in the trace). This toggles the flipflop twice, thus it is set up to incorrectly pass the next -Sector Marker pulse through and stop the write prematurely.
The issue with the first trace was a glitch during a rising edge of the generated -Sector Marker from the V2315CF in virtual mode, while the second trace shows a glitch on the falling edge. The input gate that accepts the -Sector Marker signal and inverts it for the logic diagram excerpt above has the following actual circuit values (using germanium diodes and transistors with .3V drops):
SLT logic is a form of Diode-Transistor Logic (DTL), which actually switches based on the current that sinks through the input pulling down the junction of the two diodes to cut off the conduction of the transistor. The current creates a voltage drop across the 2K resistor.
In the absence of any connection to the input pin, the transistor base is seeing a voltage well above its .3V activation level, The transistor conducts to pull the output pin down to essentially 0V. With a current flowing out of the input, the voltage drops at the junction and when it gets down to about 3.3V the transistor will be cut off entirely, letting the output pull up to nearly 3V. A 3V drop on the 2K resistor comes from an input current of 1.5 milliampere.
The nominal logic high value for the input is +3V, which means that the gate could deliver current into the input from the 2K resistor based on the voltage difference between the input pin voltage and the +6V pullup. It is possible to drive current into the power supply of the gate up through the pullup resistor. With the V2315CF, that is the terminator resistor pair dividing up the current sink between the pullup to 5V and the pulldown to ground. Since that looks like about 100 ohms, the current would be around 1.28ma.
With SLT, it is simply the pullup resistor which is often 750 ohms, reducing the current being sunk to less than 1 ma. Interestingly, the input does not have to provide a voltage at all in order for the SLT gate to see this as a logic 1 input. Unless then input pulls at least 1.5ma of current down through the input, it appears to be logic high. An open pin is the same as a logic 1 pin, other than the lack of any current backflow into the input.
While I know the exact circuit values for the components in that inverter gate above, other circuits that take signals from the V2315CF, such as -Write Clock Phase B and -Sector Marker used in different places go to SLT cards for which I do NOT have schematics. I can model the behavior of the connection from the V2315CF to the inverter for generating the -Four sector pulse output, working out termination resistor values that give proper results, I can't do that with the other gates accepting signals from the V2315CF.
Some signals are used in ways that make glitches or ringing a non-issue. -Index Marker is one where we don't care if we reset the flipflop a couple of times due to ringing. However some like -Write Clock Phase B or -Sector Marker are going to be a problem if we see false transitions.
I want the signals that arrive at the SLT input pins to be far enough from transition points or invalid voltage levels that I minimize the chance that ringing yields a transition glitch. A voltage produced by the terminator that is too low for logic high input lowers the junction voltage of the SLT inverter gate above too close to the cutoff for the transistor. A voltage that is too high above 0 for logic low input or sinks too close to 1.5ma current is susceptible to partial conduction of the SLT transistor, creating downstream glitches such as I see in the logic analyzer trace.
The V2315CF drive chip sinks the signal line to ground when the signal is logic low. The terminator resistors pull it up when it is logic high, but the SLT input gate interacts with that. There is current flow into the terminator from the SLT gate because of the +6V pullup inside the gate.
POSSIBLE SIGNAL QUALITY FIXES
I realized that I could raise the voltage of logic high input even up to 5V, having no effect on the SLT gate detection of a logic high but reducing the current sinking into the terminator. There is no cap for SLT at the nominal +3V since current does not flow into the gate from +3V, it actually flows out at the delta voltage from the input pin and 5.7V.
This leads to a choice to try a 110 ohm pullup resistor to the +5V rail of the V2315CF, no pulldown resistor at the terminator board, and observe the signals at both the input and output of the SLT gate producing the inverted -Sector Marker pulses. I will experiment with this.
The other design problem I have is the sharpness of the falling edge when the driver gate in the V2315CF switches to logic 0. The Lattice FPGA used in the V2315CF does not have the capability to lower drive current and slow down edges, so the edge going into the SN75451 driver chip is very sharp. Some ringing is caused by the very sharp edge. I can minimize it by adding a series resistor to the output line to lower the current flow, however that quickly interfees with the strategy of using a 110ohm pullup, as any resistance much above 10 ohms will cause the SLT gate to fail to see logic low because of the voltage divider between the 110 pullup and the series resistor.
I would need to slow down the signal elsewhere, perhaps in the path between the FPGA and the 75451 chip input pin. However, clean options don't exist to do that as rework on an existing board. The gerbers show that the signal line runs under the chip on the top layer and then runs in a tight group with very little spacing on the bottom layer. I highlighted the traces and circled the input pins on the 75451.
I am hoping that good impedance matching and the 110 ohm pullup will clean up the signal suitably to avoid any false transitions. I believe this will generate about 1ma of current between the +5V supply of the V2315CF and the 1130's +3V rail, assuming that the circuitry in the 2310 disk drive uses a 750 ohm pullup resistor on its output, when we are in real mode. In virtual mode, the disk drive circuit is isolated from the V2315CF.
