Interim projects while waiting on parts and supplies

BUILDING REFLOW HOT PLATE

One method of soldering surface mount parts onto PCBs makes use of a hot air gun, but that method works much better if the entire PCB is heated to nearly the melting point of solder with a hot plate, then the hot air is directed surgically to flow solder just where it is desired. 

I came across an open source design for a soldering plate which I decided to build. This one is not very large but will be adequate to my needs since I also have a reflow oven for larger PCBs. I sent the gerber files off to the fab and recently the finished boards arrived at my doorstep.

The project stated that it had a bill of materials, which wasn't quite as user friendly as it initially sounded. That is because almost every component was listed as a part number for a supplier in China, not a distributor where I could order it here. Worse, the essential details weren't listed in the BOM, for example it simply listed a part as 'diode'. 

I looked up the parts pages (in Chinese) on the supplier site and tried to puzzle out the specifications sufficient to source it from western sites. I was able to do so, I believe, although the final proof will only come when it is operational in the next day or two.

The particular gerber files produced a silkscreen with many pads labeled 'TC', other places where I had somewhat redundant names LR1, TR1, PR1 and so forth for resistor locations. The worst issue was when I began assembly, where the pad sizes were wildly different from the actual part listed. 

A set of 10nf capacitors were listed as 0403 size in the BOM but when I was ready to solder them down, I found the pads were for 1206 parts. There was too much of a gap between the copper to ever get an 0403 part soldered down. Fortunately I had a supply of slightly small 0805 capacitors of the same specification, which with a bit of care could be put into the oversized space on the board.

A voltage regulator was similarly misidentified in the BOM and was smaller than the pad layout. Again, I was able with some care and technique to get it to bond to the pads. The remaining issue which puzzles me is the third diode listed in the BOM, and shown on the schematic, but nowhere to be found on the PCB. I can improvise its placement but it is frustrating that to have to deal with so many errors. 

One element of the design is the use of an ATMEL 328 microprocessor, said part currently out of stock due to overwhelming demand. However, someone gave me a handy tip - there are Arduino nano clones from China that cost only a few dollars that contain the microprocessor on the board. A few minutes with the heat gun and I had a chip ready to install. 

I completed almost all the surface mount parts, having just 2 resistors and three diodes left to mount, after which there are switches, a temp sensor, the OLED panel and some miscellaneous hardware to go. I anticipate being ready to test this out on the bench, flash the processor with the control code and then give it a full test to temperature. 

WAITING FOR ITEMS FOR 1130 EXTENDER AND IOB6120

I will be assembling an acrylic mount and shield for the main connector fitting into the new 1130 extender case. The glue arrived today and the plastic should come tomorrow. I bought a used jigsaw and did some metal work already for the power supply mount, thus I can wrap up all the mechanical aspects when the parts are all in.

The IOB6120 needs a header to be installed on the SBC6120 front panel, with the parts coming in the next few days. Once that is ready I can test out my enhanced PDP/8 replica. 

Working on diode-resistor modifications to IOB6120

TOTAL OF FOUR ENABLE LINES REQUIRE THE DIODE AND PULLUP 

The four chip enable lines that were thought to be draining power during battery only operation are:

•  fpga enable
• compact flash enable
• flash memory enable
• status output enable

I completed the modification to the flash enable line yesterday, with the pullup resistor bridged to a nearby VCC source thus not requiring a jumper wire. I had begun on the fpga enable signal, which is done underneath the board where the traces are long enough to allow for the mod. As I previously documented, the diode and resistor were so close to each other that I kept unsoldering one as I reattached the other.

GREAT LOCATION FOR DIODE AND PULLUP FOR STATUS ENABLE

Because my diodes are much smaller than the ones done with the original rework, I could fit them in little more than the width of a trace. Thus, for the status enable signal, I had a clean location for the diode. The remaining part, a pullup resistor, could be mounted elsewhere as long as one side contacted the signal line that went to the status circuit. 

Fortunately, the enable line for the status circuit went to pin 1 of the chip, with pin 16 being VCC. That naturally supported placing the resistor between those pins on the end of the chip. I did need a short jumper because the distance was longer than an 0805 resistor.

Pullup resistor for Status enable modification

GREAT LOCATION FOR DIODE AND PULLUP FOR COMPACT FLASH ENABLE

I also found a much better location for my rework than the spot chosen by the prior rework technicians. There is a line on the front of the board between the CF socket and the coin battery holders, which is a long stretch but also has a +5V line just above it. It was relatively easy, to the extent any of these ridiculously small component placements could ever be called easy, to solder these on.

CF Enable line diode and pullup

SLIGHT RELOCATION OF PULLUP FOR FPGA ENABLE LETS ME SOLDER BOTH PARTS

The problem I had with the pullup resistor, being so close to the diode location that when I soldered one of the parts the other became loose, was solvable by moving that resistor a bit. I pivoted it around so that it projected from the +5V trace in a direction away from the diode, allowing me the clearance to solder the diode and the resistor without any negative interactions. 

Pivot of pullup away from diode above

BOARD NOW READY FOR CONNECTION, BUT MOD NEEDED TO FP6120 PANEL

The board with its 50 pin connector is ready but the front panel PCB (the FP6120) does not have a header soldered onto it. At the time I built the front panel the IOB6120 appeared to be unobtainium and further I really didn't have a need for the additional peripherals it provided. In retrospect, anything to do with a replica of an old system is by definition something without a need, so the latter factor was irrelevant. 

Now that I built an IOB6120, I disassembled the FP6120 to have access to solder down the header, once the parts arrive in the mail. From there I can put together the entire stack of FP6120, SBC6120 and IOB6120. That will permit some live testing.

POTENTIAL ISSUES WITH MY IOB6120

Since I had to buy the SRAM and flash rom from ebay sellers, there is a more than negligible risk that one or both products are counterfeits. I will only learn that if the parts fail to operate when I begin testing. 

The second issue I may face is the substitution of the 2MB flash chip for the 512KB part for which the project was designed. The protocol to load the flash might be incompatible or require some tweaking, something that has occured to others who had to substitute different parts for the 512KB flash. I will know this early on, when I try to load the firmware for the board. 

Finalizing changes to IOB6120 board for parts substitution and correction of known defect

 PART SUBSTITUTION REQUIRES A MODIFICATION

I could not find the Flash ROM part that the board was designed to use, I had to improvise with one that was as close to a drop in substitute as I could find. The original ROM is a 512K byte device in a 48 pin TSSOP layout. The substitute I found is a 2M device also 48 pin TSSOP. 

Most importantly, all the signals routed to the original part have exact equivalents on the larger flash except for the two additional address bits needed due to the larger capacity. These added signals are on pads which were unused on the original part and thus unrouted on my PCB. 

Address bit A18 is on pin 16, in between a control signal and bit A17. If I make a solder bridge then this bit will match the value of A17 and will always be a valid logic state. Similarly, new address bit A19 is between bit A8 and a pad that will still be unused with this larger chip. A solder bridge here will make A19 match the value of A8. 

Additional address pins joined to adjacent pins

KNOWN DEFECT OF REV A BOARD DESIGN

The original design of this board was known to have very high drain on the two coin batteries that retain contents in the volatile devices specifically the four static RAM chips. The defect was said to be backflow of current from the protected chips and their battery provided power, through a TTL 3 to 8 demux chip which controls four chip select signals. The chip select from the SRAM and other devices burned power in the TTL chip even when its source of VCC was shut off. 

The fix that was implemented in rev B of the board is to interrupt the chip select traces, insert a diode to block back power flow, and to add a pull up resistor on the selected chip side. This can be retrofitted to rev A boards such as mine by carefully cutting the trace of the four chip select lines, soldering an extremely small SMD diode across the gap and then soldering a tiny SMD resistor somewhere on that line for the pullup. In most cases the other side of the pullup resistor needs a jumper wire to a nearby source of VCC, but in one of the cases a nearby trace is ideally situated to directly mount it. 

Very tiny diodes shown next to a pen tip

I completed the first diode-resistor pair, for the flash chip enable, then went to work on the underside where the fpga enable diode and resistor need to be installed. The space is so tight that each time I solder on the resistor, the diode comes loose, or vice versa, so the progress is slow indeed. 

Diode on the right, 0805 resistor on the left

Set up connector for additional interrupt levels on 1130 Expander Box, tested my IOB6120 board for shorts, continuity, errors

LIMITATIONS OF IBM STORAGE ACCESS CHANNEL

The Storage Access Channel (SAC) feature for the IBM 1130 gives support for a wide range of peripheral devices to be attached to the 1130 CPU, as it offers access to memory, interrupt levels, cycle stealing and other status information necessary to create a device controller for any type of XIO operation.

Devices supported through the SAC, either attached to the 1133 Multiplexor box by SAC or directly on the connector, include 2250 graphic terminal, 1403 line printer, 2501 card reader, 2420 tape drives and disk drives such as 2310 and 2311. 

The IBM 1130 has six interrupt levels, 0 through 5, but the SAC from IBM only supports putting devices on interrupt levels 2, 3, 4 or 5, not the two highest priority levels. Some peripherals, such as the 1132 printer and 1442 card reader/punch, make use of these interrupt levels. Since IBM includes controller hardware for these peripherals inside the 1130 CPU frame, they would never be attached through a SAC. 

However, I want to be able to operate with virtual 1442 and 1132 devices, reading punching and printing with PC based files instead of real cards or paper. I had to resolve this deficiency to make full use of my expander box for the 1130. 

MY ADDITIONAL CABLE TO AUGMENT THE SAC FEATURE

I designed and built companion circuits that allow me to see and request interrupt levels 0 and 1. This is accessed by an additional cable I built and a small interface board installed inside the 1130. 

I also use this cable to route a control signal to trigger a program load sequence from my expander box. That is, it will sequence the switching as if the operator pushed Immediate Stop, Reset and then Program Load in succession. This is done with a small state machine and some relay switching of the wires that run to the console pushbuttons for those operations.

BUILT CONNECTOR ON MY NEW FPGA EXPANDER BOX FOR THE ADDITIONAL CABLE

I made use of a 3x3 connector pair to hook up the five signals that run over my additional cable, allowing me to detach that cable just as I can detach the power and SAC signal cables. To be sure I had it wired correctly, since this doesn't exist in the IBM diagrams and documentation, I carefully traced out and documented my augmented capabilities right from the 1130 logic circuits through the interface boards, cable and connectors up until the FPGA input or output terminals assigned to the signals.

As part of this work I will clean up the interface board implementation and mounting inside the 1130, now that I have good schematics and notes on everything involved with that cable. 

TESTING THE IOB6120 BOARD, WITHOUT POWER

There is quite a bit of testing that can be done to a complex board like the IOB6120 before you apply power to it. Simple tests like resistance between VCC and ground rule out gross shorts. I then checked that the power and ground was delivered properly to all the ICs on the board. I chose some signal paths and verified good continuity between the pins of the two ends.  During this process I discovered a flaw in the PCB.

IOB6120 BOARD REVISIONS AND REWORK ACCORDING TO OTHERS

There is a second version, Rev B, that is said to correct a design flaw that leads to rapid depletion of the backup batteries which preserve data in volatile memory devices. The cause of the depletion was said to be due to back flow of the battery current into a chip that is not part of the nonvolatile memory system. The solution to this was the creation of diodes with pullup resistors to isolate the chip enable lines of the nonvolatile chips from the enable driver chip - a total of four diodes and four pullups. 

Revision B has this implemented while the original does not. A rework is possible by cutting the chip enable traces, tacking on a diode and pullup resistor then routing VCC to the other end of the pullup resistor. I was prepared to make this change to my board, but discovered something during my bench validation of the board which I believe was missed by others.

The original board failed to route VCC to a pin of one IC, a BQ2201 nonvolatile memory controller chip. This device is connected to the battery backup voltage as well as the power-on VCC rails. It compares the voltage and will block the chip enable to the volatile RAM chips if the VCC drops below 4.67V. It also switches the two coin sized backup batteries onto the power rail for the RAM chips. 

With this unpowered, the chip will ALWAYS block the chip enable and hook the batteries up to power the circuit. That chip enable gates the 3 to 8 demultiplexer so that the board should not be able to work at all with that trace unconnected. I soldered in a jumper to deliver power to the pin - and do see that the rev B correctly routes power to it. 

Jumper bringing VCC to IC14 - BQ2201

Another teletype weekend, time off from my projects

MACHINE 3 PARTIALLY FIXED, WAITING ON PINFEED FORMS

The keyboard was properly adjusted and was the typing unit distributor and selector properly serialized and deserialized the typed characters. The type quality was excellent with the new ribbon installed. This machine has a form feed option where it takes forms with sprocket holes, the inner forms are 8 1/2 x 11 in side.

The form feed mechanism was initially frozen in place, but eventually loosened. The machine would take cycles for Line Feed character but not for Form Feed, also it was not yet advancing one line or form with that cycle. The rest of the typing functions seemed fully operational. 

The owner has ordered a roll of the paper but chose to put the machine aside until we have the proper paper with which to continue testing and adjustment. As a result, we didn't finish the line/form feed fixes, nor work on the paper tape reader and punch parts of the machine.

ASR/33 READER POWER SUPPLY FIXED FOR MACHINE 1

The ASR reader makes use of 150V DC to power the solenoid that tests the holes and advances the tape on sprocket hole. This was blowing fuses when we last worked on it. After some false leads of the root cause of the overload, where we replaced the rectifier diodes and main filter capacitor, we discovered that we had some gunk on the PCB that was conductive enough to pull more than 1A even with no load wired to the supply. With that fixed, the supply worked great. 

USING EXTERNAL 20MA TO RS232 ADAPTER ON MACHINE 1

We had initially worked on the machine in Local mode where the output of the keyboard is looped back to the typing unit so that each keypress results in typing or other functions on the machine in front of you. More typically, these are attached so that the key presses are sent out over lines to a remote teletype or computer, while data from that remote location comes back to the typing unit to be printed. This is Line mode.

The owner brought a small box that supplied 20ma to the typing unit and read the keyboard side, using a RS-232 serial connection on the other end. With that we used an oscilloscope to watch the well formed serial data stream during keypresses and then looped the RS-232 RX-TX for local printing of what we typed.

MACHINE 1 MOST PROBLEMS RESOLVED

We had a list of problems for machine 1 when we began this weekend, among them were failure to line feed, carrier return not getting all the way to the left margin leaving the carriage unlocked, printing only the right edge of each character, and the reader wasn't operating. 

The line feed issue needed a small adjustment to pull down far enough to rachet the platen up one line. In addition, the line feed operations triggered most time but not every time an LF was sent. That will involve a minor adjustment of the triggering mechanism, but we didn't get to it this time.

The carrier return latching issue was due to crude on the piston and cylinder on the left side which cushions and slows the carrier as it returns. A long spring provides the energy to pull the carrier to the left once it is unlatched. As the piston seats in the cylinder a projection on the carrier moves a mechanism to relatch the carrier. When the piston didn't seat all the way, the carrier didn't relatch so we would type characters atop each other with no rightward carrier movement.

I cleaned and oiled the piston and cylinder, cleaned the rod upon which the carrier travels, and lubricated the rollers and bearings that support the carrier. With that done, the carrier return would completely enter the cylinder and relatch. 

The adjustment for the partial printing is to loosen the nut holding the type cylinder in place, turn it slightly to make the full character face the platen, then tighten it up. We did see the type quality improve greatly, but the cylinder would soon slip out of position. A new lockwasher didn't improve this enough, so it will need to be attended to in the next session.

Inside the paper tape reader is a microswitch that turns on the reader. There are two types of readers on ASR-33 teletypes, automatic and manual. This machine had the simpler manual version which just reads continually as long as the lever is turned to the on position of the reader. A pin pops up to sense whether there is paper tape in the reader, if not it blocks the contact even though the lever is set on. 

When the lever is on and the pin detects paper, the reader closes a solenoid inside the typing unit which trips the distributor clutch and the large solenoid in the reader pushes spring loaded pins up in the eight data positions across the tape. Everywhere there is a hole, the pin goes up and makes electrical contact.

As the distributor clutch cycle begins, a microswitch interrupts the large solenoid power to the reader, which pulls the tape to the next sprocket hole position. When the distributor cycle completes, having serialized the character from the tape, the microswitch again allows the big reader solenoid to be energized. 

Thus we have a synchronizing dance of the little solenoid triggering the distributor clutch to transmit a character, the microswitch releasing the big reader solenoid to advance the tape on position, and then the microswitch reconnecting at the end of the current character to read the next. 

We were not seeing the big solenoid pull and release but all the voltages and contact circuits were working properly. The solenoid shows as the 100 ohm DC resistance that is expected, so our next session will first verify that the magnetic field is generated before we begin readjusting the solenoid to properly move the mechanisms in the reader.

140,000 PUNCHED CARDS PICKED UP BY NEW OWNER

Since I had reliably read and archived all the card contents of my large collection of 1130 oriented punched cards, it was time to free up the room in my workshop that they took up. The new owner arrived with a box truck and collected them all on Saturday.

All receive and send circuits of 1130 Expander tested, LEDs fixed, finished assembling IOB6120

FIXED THE THREE RECEIVE CIRCUITS THAT DIDN'T WORK PROPERLY

Yesterday I tested each circuit to verify that when the input wire from the 1130 is pulled low, the circuit outputs +5 on the pin going into the FPGA for that signal. Three of the 36 circuits did not respond correctly, in two the signal didn't get past the 500 ohm output resistor and in one case I didn't see the output on the transistor.

All of these were resolved by a quick touchup with the soldering iron. Solder didn't flow between the PCB pad and the component, in all three cases, instead blobbing up atop the component and appearing superficially correct. 

DEVELOPED TEST PLAN AND CHECKED OUT ALL SEND CIRCUITS

The send circuits take a logic low from the FPGA, which has those outputs operating with a weak pullup, inverts it and pulls down the output line to the 1130, which is also open collector. Thus, I needed to add a pullup resistor on the output lead I was using to check each circuit, then connect the FPGA pin associated with that circuit to ground. 

I found all send lines pulled to ground in the absence of the ground input, but they all popped up to +5V when I grounded the inputs. In practice, the 1130 supplies a pullup to +3V for those output lines, so the actual behavior will be 0 when the FPGA sends high and +3V when the FPGA is at logic low. All forty send lines were working perfectly. 

SWITCHED LEDS OVER TO 12V SUPPLY AS THEY WON'T LIGHT WITH 5V

The LEDs would not light with proper voltage applied, if you remember. I hooked them up directly to +5V through a load resistor and got no glow at all. I then tapped into the +12V that is delivered by the PC power supply and we had illumination! The load resistor that worked well is a 200 ohm part. I swapped the SMD resistors on the PCB from 90 ohm to 200 ohm.

The LED that should light simply because the power supply is active was hooked to the Power Good pin of the supply, but that is not a high enough voltage. Instead, I hooked up the three LEDs (Box Power On, CPU Run and CPU Parity Check) to the +12V supply, adding a connector to allow disassembly during future maintenance. The Box Power On LED is always grounded through a 200 ohm resistor, thus it turns on as soon as my box is plugged in. 

The two signal reporting LEDs - CPU Run and CPU Parity Check - are triggered by the input signals received on the A5 and B8 circuits. I manually tested and when I ground the input terminals, the LEDs glowed properly. The last LED is hooked directly across the 1130 power sequencing lines, which is at 24VAC when the machine is turned on - I previously verified that this one will light in that situation. 

SOLDERED REMAINDER OF IOB6120 BOARD TOGETHER

I soldered the remaining fourteen surface mount integrated circuits and then all the through hole parts which were mostly connectors. After I soldered each chip in place, I used a tiny screwdriver tip to push on each chip lead. Any that moved were resoldered until all connections were known to be good. 

SOME ADDITIONAL WORK REMAINS FOR THE IOB6120

Since I substituted a larger flash ROM for the one in the design, I have an address line or two that may be floating as the board was designed. Fortunately all the pads match between the two versions of the chip other than some address lines which are on pads that were unassigned in the design. After I check the pad to see whether it is connected to anything, I will make sure the line is routed to ground to ensure good operation of the flash chip. 

There is a fix that has to be applied to the version of the board that I built, because the original design will drain the two 3V coin cells too quickly. This involves hooking up four diodes and four resistors, cutting traces and perhaps adding a short wire or two. 

OPEN QUESTIONS

Since I had to source components, particularly the flash ROM and the four SRAM chips, from eBay sellers there is the possibility that I was sold counterfeit chips. If these were not SMD versions I could have easily breadboarded up a test of the chips, but that is quite inconvenient for the surface mount versions. We shall see what happens when I attempt load the flash, program the FPGA and then have them access the SRAM. 

Designed power supply mounting, did some wiring, finished 160 pin connector wire extenders and now testing

POWER SUPPLY MOUNTING DESIGN

I have only enough room for a mini-ATX power supply in the case. There is about an inch to spare in width and height, more room front to back. I am using an extension that puts the power outlet on the rear of the case and then allows it to enter the PS on its side. 

The power cord is routed above the edge of the PCB, around the entire PS and then to the rear plug. The output cable from the supply also wraps around the entire PS before plugging into the PCB. The other output cables, typically connected to disk drives in a PC, are just placed in front of the PS in the empty area. 

The power supply has four 6-32 screws that fasten it to a PC frame, on the same side as the power socket. I worked out a design for a bracket, made by bending a 6" x 5" aluminum sheet to form two 3x5 planes at right angles to each other. On one plane I will cut out a center rectangle for the power socket and air entry, and drill the four holes for the PS mounting screws. The other plane gets two holes that match existing studs on the bottom of the case I am using. 

HOOKED UP LEDS, 24VAC CONNECTOR

I neatly wired up the four LEDs to the PCB screw terminals, then began to test out the lights. I first applied 24VAC to the circuit that shows the 1130 power is on - that worked fine. Next, I turned on the power supply expecting the second LED to light showing that box power is on. It didn't light. 

I measured 5V at the wire going into the LED but it didn't light. I have to investigate further - I was pretty sure that these LEDs would light with a lower voltage drop than the 5V I see delivered by the supply. Although, it might have a high internal resistance since I am tied to the power good output of the PS whose internal design is not known. I will do some more investigating on the next visit to see what is going on with the LEDs. 

When the 1130 powers on, it sends 24VAC out through the power connectors to each attached peripheral, intended to energize a relay to power up those attached boxes. I wired up the 1130 power connector socket on my box to the small connector on my PCB, so that when the 1130 turns on, it will light the leftmost green LED. 

COMPLETED THE WIRE EXTENSIONS FOR THE MAIN SIGNAL CONNECTOR

I finished adding all the 6" extensions for the output signals from my PCB to the 1130. I should be able to easily connect all the lines to the screw terminals on my PCB. After adding the extensions, I checked each and every wire to be sure that the labeled connection is hooked to the proper pin on the signal connector. There are 160 pins on the connector but only 77 active signals, the rest are either ground or unused pins. 

I have labeled the lines by the FPGA board connector pin they route to - there are two 2 x 32 pin headers that attached the board to my PCB. Each row is assigned a letter, thus the left header (viewed from the front of my board) has rows D and C, the right header has rows B and A. Vertically from the bottom of the board they are numbered 1 to 32. Some of the pins are used for power, ground and other purposes, but most are input-output lines to the FPGA.

For example, the outputs from my FPGA to the 1130 computer are assigned to rows C and D. Thus there are signals like C3, D3, C4, D4 etc. The inputs to the FPGA that monitor signals outputted by the 1130 are assigned to connections such as A4 and B20 on the other header. My wires have labels like A5, but they are hooked to 1130 signals, in this case CPU Meter Out which is also named CPU Run. That is wired to pin E1 of the 160 pin connector. 

I worked through all of the signal wires, verifying that each labeled FPGA connector pin went to the proper pin of the main signal connector. I also checked that the FPGA connector pin is tied in my VHDL code to the appropriate 1130 signal - so that A5 is indeed read as CPU Meter Out. 

I had spotted a swap between the assignments for two signals - CPU Parity Stop and X2 Clock - which were assigned to A8 and B8 but swapped in meaning. I corrected the labels and updated my documentation. All is now correct. 

TESTING TO ENSURE ALL IS WORKING PROPERLY

I checked that appropriate power is delivered everywhere it should be - 5V, 3.3V and 3V - and that it didn't appear on any signal pins. I tested for shorts. I validated that the terminals for received signals all had the expected resistance and voltage. The terminals for sent signals are open collector so they didn't have any output voltage. 

The received inputs are pulled low by the 1130 when they are asserted - logically true - and my receive circuit provides a pullup to 3V just to ensure there are not false positives. It is the same circuit that IBM implements for such signals sent over long cable runs. Because of this, I could temporarily ground each receive screw terminal which should flip the output on the FPGA header pin from 0 to +5V indicating the 1130 signal is true. 

I did this for all 36 received signal circuits and found three that weren't switching. Two of them switch at the output of the transistor on my receive circuit but are not making it through the 500 ohm coupling resistor. The third doesn't turn off the transistor regardless of the input signal. 

It should be easy to track down and fix those circuits. I then have to do the same thing to test my driver circuits which are simply high current open collector inverters. I can't see the outputs without adding a pullup resistor to the screw terminal, then delivering +5 and 0 to the FPGA pin associated with that circuit. The 0 input should let the output pull up to high, while a high input should drag the output down to ground. 

Once I know that all inputs and outputs work properly, I can finish the assembly and do a power on test with the FPGA board connected by USB link to the PC. 

PARTWAY THROUGH BUILD OF IOB6120

Since I received my PCB blanks from the fab yesterday and have all the parts in the shop, I started to assemble the board. I soldered down some very small parts first - a flash ROM and a Xilinx FPGA chip - then put on all the SMD resistors and capacitors. There are about a dozen ICs to add and then the through hole parts before the board is complete.