Fully vetted original card at full speed using rig to diagnose backup card and working on power sequencing problem

FULL SPEED TEST OF ORIGINAL 6213 CARD

I moved slowly and carefully through a full set of tests of the original 6213 card while driving it with a 2.25MHz square wave, the same speed as the oscillator card for this 1130 model.  I looked at the existence and quality of the output signals such as the pulses that cause the T or X clocks to advance and the Phase A and Phase B clock signals used throughout the system. 

The card went through its paces responding properly to all the conditions to start and stop the processor, implementing various debugging modes such as Single Memory Cycle, handling all the situations that require multiple T7 cycles, and managing the system wide reset lines. 

It is now mounted in the IBM 1130 and ready for some in-system debugging once I correct the power sequencing issue it is currently exhibiting. At this point, any failure to go into or out of Run condition or other actions handled by this card would be causes outside of the card itself. That helps in debugging.

SPARES 6213 CARD TESTED IN RIG

I switched over to the spare card, since the museum stripped down a second 1130 to build an inventory of cards just in case they needed a replacement. I put it through its paces as well. Interestingly, it is almost working perfectly. It handled every condition well except one. When the operator Reset button is pushed, the DC Reset signal that resets the machine state oscillates between 0 and 1.3V. 

The output circuit that drives the DC Reset lines is a paralleled set of high transistors in an High Power Driver (HPD) SLT module, suitable for a fan-out well over 100 destination gates. It is fed by an And-Or-Invert (AOI)  module plus an And-Or-Extend (AOXb) module. The AOXb implements one of the AND gates on the ALD page, the AOI implements the other and the AOXb is fed to the Or input of the AOI so that the pair implement a pair of ANDs feeding into an OR. 

The inverted output of the OR is fed to the HPD, which itself inverts, thus the resulting signal is positive sense. If either AND condition is true, the HPD driver emits a high output. Low output resets all the gates fed by this signal, as the actual signal is -DC Reset. 

Both AND gates receive a copy of the -Power On Reset signal, thus if this signal goes low the DC Reset is activated. -Power on Reset is generated by a relay in the power-up sequence that is switched on after a several second time delay, intended to allow the power supplies to stabilize. 

One gate of the pair, through the AOXb, is fed the -Reset signal that goes low when the operator pushes the Reset key. The other gate is fed the +Run/Prog Load Dot on Run signal. The result of this logic combination is that the machine will reset while -Power On Reset is low (at power up), then will reset only when both of the other signals are low. Essentially, the Reset key only takes effect while the system is stopped. 

The operator boot keypress sequence is three keys in order - Immediate Stop, Reset, Program Load. The Immediate Stop is necessary to reset the run condition otherwise the reset won't work, and the Program Load depends on the initial state of the machine caused by Reset. 

The problem is occurring while the machine is stopped and reset is activated, but works reliably when the -Power on Reset is active. This tells me the issue steps from the feed from AOXb to the AOI or something in one of those two modules.

I initially did a diode and resistance check of the relevant pins in the two modules. I also checked them against other AOI and AOX modules on the card. I did not find any discrepancies through this method. Therefore I have to dig deeper. 

POWER SEQUENCING ISSUE

The power-up sequence logic of the IBM 1130 applies power to the main rail supplies then waits for the three levels to come on. An SMS card is fed the +3, -3 and +6 voltages which activates three reed relays on the card. The contacts of those three are wired in series to connect a circuit only while all three voltages are present. This circuit activates relay R1.

The contacts of R1 are responsible for two things. First, they activate relay R2. Second, they enable a hold circuit on the SMS card through a reed relay RR1 on that card. Upon power activation, while the power supplies were coming up to power and the above steps were occurring, a time delay relay TD-1 was also activated. This trips in about 5 seconds. 

If TD-1 trips while relay R1 is not active, this means that we don't have all three power rails. The consequence of this is that the main power contactor drops out, but it also powers the hold relay RR1 on the card. RR1 has a contact that holds it latched thus disabling the power on switch from attempting to power the machine again. 

In brief, if after 5 seconds the three power rails were not present, the machine shuts down and locks itself out due to the hold circuit. One has to flip a hidden CE Switch, turn off the main breaker or unplug the machine from the mains to drop the hold relay RR1. 

Meanwhile, assuming that R1 activated because we have good power, relay R2 is activated also. It passes the +12V and +48V supplies to all the loads they feed. These are needed to power core memory, the pushbuttons and lamps beside the keyboard, and solenoids on devices like the keyboard and console printer. 

You can tell when R2 activates because the Power lamp near the keyboard illuminates. On this machine, that does not happen. Something is going wrong in the power up sequence.

I verified that the SMS card is engaging the circuit when all three rails are present. This is when I ran out of time for the day.

Next up, I have to verify that R1 is engaging, then that R2 engages, and finally that the two final voltages are delivered to their loads. I also need to see TD-1 engage and allow -Power on Reset to go high.