Power problems ironed out, continuing both system and card debugging

WORKING ON THE SLT CARD TEST RIG AFTER DIGGING INTO ONE FAILURE I SAW

When I was running the card in Single Storage Cycle mode (SMC in some documentation for Memory Cycle), it should reset the Run flipflop when T7 clock state occurs. Specifically, the signal -T7 is fed to an edge triggered circuit, so that if the circuit is gated by a logic 0 on -Single Storage Cycle, it will sense a pulse to zero on the DC Reset input of the Run Flipflop. 

A similar failure occurred when a second circuit, also fed -T7 as a trigger, is gated by a logic 0 on -Wait Not Stor Load/Display. These two edge circuits are both implemented on a single RC Module (type 2390709) which has 33pf capacitors from the trigger and a 2.5K resistor from the gate, both feeding to a central point that is the output which is wired to the flipflop DC reset pins. 

I put the scope on the outputs of the module and saw nothing when the trigger went low. I pulled the module out of the card and checked its components, but it was solid as could be. I then checked all the diodes and transistor junctions in the Run flipflop but they too looked correct. 

RC Module removed from board

2390709 RC Module

Unlike other signals fed to different edge triggered gates, T7 is one of the few complementary signals where both the positive and inverted sense of the signal are fed to the card simultaneously. There is a +T7 and a -T7 input pin on the card.

For the complementary signals, I was feeding them from a pair of DIP chips on my breadboard - a hex inverter and a hex buffer - so that one input to the pair of chips would generate the complementary states as output. When I looked at the logic 0 output levels of those chips, I found that it was just above 0.3V. 

As a test, I hooked -T7 to a switch that directly connected it to ground when activated. The edge trigger fired and the Run flipflop was reset! My test setup was not pulling the node attached to the capacitor far enough down to create the desired output. 

I pulled out a relay board and used that to generate the complementary high and low logic levels for each of the complementary signals that are used with edge triggers inside the card. That did the trick and I was able to walk the card through all its paces. 

I carefully tested that each input caused the appropriate behavior in the card. A number of conditions cause the machine to take multiple T7 steps before starting the next memory cycle. Among them are arithmetic, shifts, and some cases of conditional branches. When any of these exist the machine does not start on the next memory cycle (at T0) until the condition is released. 

The machine will stop when a parity error occurs or when the CPU is stopped by the stop latch. This can be due to the Immediate Stop operator button or a wait instruction. The stop is processed at the end of a instruction cycle after the machine tests for any pending interrupts. The -Set Interrupt SP signal triggers the check of the stop condition; that worked perfectly as well. 

If the machine is stopped but an interrupt request arrives, it should go into Run state to execute the interrupt handler. This is triggered by the -Interrupt Request signal and it checked out when tested. 

When the Program Load button is pushed, circuitry will block the Run condition from coming on for instruction execution, but the machine is taking storage cycles to store the boot instructions coming from the boot device. These are triggered by pulling the -Delay output low (signal -Prog Ld T7 Phase B)

The block is released when a response arrives from the boot device that the data is complete. For paper tape it is a particular hole pattern, but for the card reader it is the end of the one boot card that signals completion. Relieving the block causes the processor to fetch an instruction from location x0000 and execute it. The block is -Prog Ld Not SRP or PT Resp (note an old internal name for the 1442 card reader is SRP). 

An additional signal that will stop the machine from advancing from T7 to the next storage cycle at T0 is the signal -CS Levels. Cycle Steal is IBM's name for direct memory access, which is managed by a second clock ring X0 to X7. This signal blocks the T clock from running while the processor is accessing memory using the X clock.

WILL DO FINAL FULL SPEED TEST OF CARD TOMORROW

I will hook the card up to the 2.25MHz square wave output of my function generator and test out is functions once again, just to be sure we don't have any subtle failures that only occur with brief pulses. I should see the +Phase A and +Phase B signals being emitted, the -T Clock Advance Sample and -T Clock Adv SP signals come out each time the T clock should advance, and suitable pulses be emitted for the -Phase A SP A output. 

Once that works, any problems with the Run condition staying on has to be caused by one or more of the inputs to the card, which I can quickly run through using the oscilloscope. 

I PLAN TO BEGIN TESTING THE SPARE CARD IN THE TEST RIG

Since the failure I saw in the spare card, failure to respond to the Prog Start complementary signals, might be similar to the issue I fixed with the relay modification to my breadboard, I will retest to see what persistent errors exist and debug from there.

REPLACED FUSE HOLDER AND REINSTALLED POWER SUPPLY

My local hardware store had panel fuse holders in stock. In short order I replaced the holder, inserted the fuse, reinstalled the supply and wired it up. 

DEBUGGED AND FIXED LACK OF +12V TO SYSTEM

The failure was clearly on the SMS power validation card, relay RR-1 which is triggered and holds itself energized when the three power rails (+3, -3 and +6) are present. That has contacts that energize relay R2 inside the power distribution box. That larger relay switches both +12 and +48 voltages onto the logic gates of the machine. 

Without this relay engaging, we don't get the voltage needed to properly sense the operator control buttons and mode switch. Nor do we have the voltages needed to read and write core memory, thus it is a good thing that we don't have the clocks running. 

When I received the machine, some prior restorer had replaced an IBM reed relay on the SMS power sensing card with a solid state DIP replay. I tested the IBM relay, found it good, and returned the card to original state. 

Unfortunately, the relay was misleading me and has failed (again). I restored the solid state relay and verified that the card now produces the right signal indicating good power levels. 

TWO PAGES OF ALD FOR THIS CARD ARE BELOW, FOR THE CURIOUS