Diagnosing memory parity error on VCF 1130 - fixed and working well

SYMPTOMS

Whenever address bit 9 is a 1, the machine gets parity errors, regardless of the remainder of the address bits. As a refresher, bit order on an 1130 is bit 0 leftmost, with the highest value and bit 15 on the right of the word is the least significant bit. Thus we are talking about addresses of the form xxxxxxxxx1xxxxxx where X means the value doesn't matter. 

BUILT PLAN TO LOOK AT ADDRESS BIT 9 AT VARIOUS SPOTS

Bit 9 is generated in the B gate, compartment B1 and then runs by cable over to B gate compartment C1 where the memory is located. In the memory compartment the bit in question enters at a cable connector in slot A1 pin C09. 

That signal, -SAR bit 9, is also inverted by a board in slot F2, since the logic in the memory uses both +Sar bit 9 and -Sar bit 9 to choose particular memory line drivers. 

I would look at the bit in B gate compartment B1 as well as in C1 at the entry connector and the inverter card. I did check the signal connectivity from the inverter card pins to the driver board pins that are responsible for handling bit 9, which was fine. 

There are two cards at G3 and H3 which produce the Y axis selection for one of eight sets of 16 addressing lines for all the entire 8K array. Each card handles four of the eight cases; for example, card G3 handles bit 9 being 0 and the four combinations of address bits 10 and 11. For a given binary pattern of the three address bits 9, 10 and 11 there is only one group of sixteen address lines which should be connected.

The connection is through a diode matrix and the card will either connect its sixteen Y lines to the +8.3V drive power if writing or sink the current on those lines if reading, since we reverse the direction of current flow between writing and reading. The Y axis has 8 sets of 16 line groups such as we are selecting with our two cards. 

The other end of those 16 line groups are tied together, the first line of each group together, the second line of each group tied together to a different common line, etc. The common lines are thus just sixteen for the entire Y axis, with cards that choose which of those sixteen common lines are active by address bits 12, 13, 14 and 15. Thus our bits 9 through 15 select one of 128 wires threaded in the Y axis.

The X axis is a bit simpler, with bits 3, 4 and 5 picking one group of 8 wires out of eight groups, then the bits 6, 7 and 8 picking among 8 common lines analogously to how in the Y axis we picked among 16 common lines. Having 64 X axis wires and 128 Y axis wires allows us to select one of 8,192 core positions or words. 

STRANGE CHI BOX INSIDE THE MACHINE IS WIRED UP TO MEMORY!

The machine has a thin aluminum box mounted to the wall of one of the gates, with a switch on top that is labeled CHI-IBM. There is a long cable coiled in the machine with a card edge connector at the far end. Previous guesses about this box was that CHI, a third party maker of modifications and peripherals for 1130 systems, used this either for another disk drive or for a third party printer. 

Box pulled from side of gate to investigate

However, as I examined the connections that made into the machine, I found that these were directly interfacing to memory. They grab the output of core sense lines, read the B register and look at the addresses and the storage read/write line. 

Connectors at top

Various plugs and connectors

I turned my attention to the inside of the thin box, which had a PCB with a number of logic chips. I didn't have to reverse engineer it far to discover that the chips are powered over the cable with the remote connector! No external box, no power. These chips are wired into the 1130 but it can't implement its "CHI-IBM" selection with no power to the logic!

REMOVAL OF THE THIRD PARTY MEMORY MODIFICATIONS

I studied where they were connected to determine if they had cut traces on the boards of the 1130 or otherwise made changes to the machine. It appeared that they only had the connectors onto the board and to various pins on the board - these could be pulled off. 

I therefore removed the entire CHI installation. Without the other box it was intended to connect to, this is useless. Further, it may be introducing the memory problem we were experiencing. 

RESULT - NO PARITY ERRORS AT ALL

When I tried the machine without the CHI connections, it worked perfectly. All memory is usable and as a bonus we even got the IX cycle back as a bonus. That was the problem where instructions that referenced index registers were not taking the IX memory cycle necessary to read or store the index register. Index registers on the 1130 are simply core memory address 0001, 0002 and 0003, thus a memory access cycle is needed to get to the index register.