More testing of the cycle steal (DMA) core memory loader

NOT HAPPY WITH TRIGGER AND STOP OF THE CYCLE FROM THE ARDUINO

I discovered that the logic wasn't doing what I expected - wait to trigger until the Arduino request line (ArdReq) goes high, emit a done line (ArdDone) to the Arduino, then go back to idle when the ArdReq line is dropped. 

I did spot the reason for the flaw and believed that a very simply change would fix it. I worked out a mod I could make to the board, cutting one trace and adding a wire between a couple of other pins. I applied this bodge to the board and tested again. The start and stop of the cycle steal was now reliable and just as I intended.

CHECKING THAT ADDRESS AND DATA EMITTED TO 1130 ONLY DURING A CYCLE

I hooked up some wires to address and data pins on the board, as they would be raised by the Arduino before commanding each cycle steal. I then monitored what was done to the wires that will be connected to the 1130 circuitry. 

Since the gates driving the 1130 are open collector, intended to interface with the different voltage levels of SLT versus TTL, I also put in some pullup resistors so that I could observe the actual logic state of these output pins. 

I worked through all of them, ensuring that I would present the address and data correctly to the 1130 system. I also verified that control output lines -CSLevel0Request and -FileGateEntry were asserted (pulled low by open collector gates) at the proper time during a cycle steal.  

CHECKED OPERABILITY OF THE TTL LOGIC WITH SLT CIRCUIT INPUT SIGNALS

Since SLT logic has a different voltage scheme with an on state nominally +3V and off nominally 0V, while TTL has +5 and 0 for its nominal values, I wanted to be certain that a valid SLT logic level would be detected properly by my TTL logic gates. 

I did not find a complete set of lowest valid high and highest valid low voltages, but IBM did specify the 'transition' voltages where a rising signal switches from 0 to 1 and where a falling signal switches from 1 to 0. These are 0.3 and 1.8V respectively.  Thus I can expect SLT to give me something below 0.3 when low and above 1.8 when high.

SLT operates only by sinking current, as far as the input of the next gate is concerned, not the actual voltage level. If the output voltage is low enough to cause a current to flow from the next gate input down through the output to ground, then it is at logic low. Any other condition is logic high. Thus an open circuit is a valid high as far as SLT is concerned, with 0V present. 

The typical gate output of SLT is formed by a transistor whose base is tied to ground and whose collector is the output. A pullup resistor, often 5K, brings the collector up to +3V when the transistor is not switched on. The germanium transistor has a diode junction voltage of about 0.3V, thus when turned on it appears to be at roughly 0.3V. 

That means my TTL gates will see about 0.3V when the driving SLT gate is in the low state and about 3V when the gate is in the high state. If the SLT gate is also driving other circuits then resistor divider effects could lower the sensed voltage somewhat, but it is going to be well north of 2V for any practical case. 

Going in the other direction, an open collector TTL gate could sink perhaps 8ma to near ground level, which is certainly enough to pull the junction of diodes inside an SLT gate down to zero volts as they have resistors on the order of 2K pulling the junction up and about 5K pulling down and therefore only need a bit over 2ma of current sinking. 

Even considering the non-zero output because of the diode voltage of the TTL transistors, SLT is implemented with -3V and +6V rails plus a few diodes such that the voltage at the base of the SLT inverting transistor is below its threshold even when the inputs are a bit above 0.  This means that our TTL open collector gates can easily inject a logic low into an SLT circuit. 

Thus, I checked whether my TTL gates would work properly with inputs down to 2V for logic high and with inputs a bit above 0.3 for logic low. The specification for most 74LSxx gates is a minimum of 2V for logic high input and a maximum of 0.7V for a logic low, which fits nicely with the expected situation. My circuit breadboard tool has a variable supply allowing me to adjust the voltage being fed into my circuits, seeing them detect properly with 2V and 0.7V levels presented on their inputs. 

FINAL BOARD DESIGN SENT TO THE FABRICATION HOUSE

I worked carefully on the board, cleaning up traces, adding extensive ground planes and improving the silkscreen legends. Now that the logic is working as desired, I uploaded the design to JLCPCB.com and will wait for the final boards to arrive in a week or so.