Put instructions through their paces and the 1130 and CPU appears very health; one annoyance returns

HAND ENTERING ALL THE INSTRUCTIONS TO SEE IF THEY WORK CORRECTLY

I toggled in instructions and test data, one at a time, then executed the instruction to validate the expected behavior. 

The load and store instructions, both single word which pertain only to the Accumulator (ACC) register and the doubleword versions which deal with both ACC and the Accumulator Extension (EXT), did exactly what they should. The same was true for the Load Index/Store Index and Load Status/Store Status instructions. 

Shift instructions come with subtypes. When shifting left, one can shift just the ACC or shift the combined ACC and EXT. In the latter case, bits shifting left out of the high order bit position of EXT are inserted as the new lower order bit of the ACC, thus this is treated as a single 32 bit data item. 

There is a variant that is Shift Left and Count, where it shifts bits leftward one at a time until the high order bit position of the ACC is a 1. While it is doing the shift it is decrementing a count field, typically in an index register, so that the instruction will find the position of the first non-zero bit in the ACC. It can operate on ACC alone or on ACC + EXT. 

When shifting right, one can shift only the ACC or shift both ACC and EXT as a combined 32 bit value. As bits are shifted to the right, 0 bits are injected into the high order position of ACC. Finally, there is a version called rotate right which shifts both ACC and EXT, taking the low order bit of EXT and putting it into the vacated high order bit of ACC. This moves a 32 bit value circularly, with no loss of bits. 

Three broad version of branching exist. The Branch and Store IAR (BSI) is used to call subroutines, because it stores the next sequential address after itself in the first word of the target location and then starts executing at the second word of the target location. The subroutine can branch indirectly through that first word to return to its caller. 

The Branch or Skip on Condition instruction will change the next instruction to be executed based on selected conditions. For example, the short version of BSC will fall through if the conditions are not matched but if any of the selected conditions exist, it will jump over the next instruction and instead the instruction one location further. The long version branches to a target location or executes the next sequential instruction. The branch occurs if none of the selected conditions are matched, in a sense the inverse of how the short form works. However, in another way it is the same, as we either skip if any condition is true for short form or skip the branching if any condition is true in long form. If we don't skip, we execute the next sequential instruction after the BSC. 

The Modify Index and Skip (MDX) instruction, short form, does arithmetic on the IAR or one of the three index registers. If the result in the register after the arithmetic is zero or changes signs, it skips the next sequential instruction. If the IAR was changed it is just a jump to that location. The long format works similarly, except instead of updating the IAR, it adds to the value in a memory location or updates index registers. 

I didn't find any instructions that didn't work exactly as they should, but this was still not a comprehensive test. That will take place when I run the CPU diagnostics. 

PARITY ERROR BACK WHEN ADDRESS BIT 9 IS A 1

The issue is back. I had hoped this was simply caused by the CHI modification which I removed, but clearly it is not. This is the next area of restoration work.