Will be testing the 3132 SLT card as I troubleshoot the memory parity error issue

MEMORY BEHAVES AS IF IT IS NOT BEING DRIVEN FOR THE ADDRESS BIT 9

In the 1130, one parity bit covers eight of the 16 bits in a word and a second bit covers the remainder. The scheme for error checking is that there must be an odd number of 1 bits in each half of the word - if the data value has an even number, then the parity bit is set to 1 so that the 9 bits always have odd parity. 

The parity error we receive for any memory address where bit 9 is 1 shows up as reading a word of all zeroes plus both parity bits are read as zero.  Violating the odd parity rule, we lock up with the error. This is the kind of output one would get if the memory was not actually read. If the cores aren't flipped then the sense lines never detect the pulse that occurs when a core had a 1 stored in it. All cores appear to have had 0 in them, but in reality it is likely that we simply didn't flip the cores.

THINKING ABOUT POTENTIAL CAUSES FOR THIS FAILURE

All other addresses work perfectly so we know that most of the memory circuitry has to be okay. We are just not driving the current through the wires the are activated when bit 9 is a 1. There are four groups of wires that could be driven with bit 9 is on, the individual group actually used is based on bits 10 and 11. Then bits 12 to 15 select which of sixteen wires in that group connect to form the single wire through the core stack in one axis. Bits 3 to 8 select the other axis such that one and only one core is at the intersection of those wires. Multiply this by 18 core planes, one per bit of data or parity. 

The selection logic has an AND gate which is wired to bits 9, 10 and 11, either the inverted or true version of them in order to activate the assigned group of wires. Thus when bit 9 is a 1, there are four AND gates with true bit 9, the other inputs being combinations of true and inverted bits 10 and 11 to cover all four cases. 

One of four AND gates driving read drivers for bits 9-11

The input address comes to the memory in inverted form, therefore it only receives -Address Register Bit 9 and the true form has to be generated using an inverter (NOT gate). 

Inverter on card F2 for address register bit 9

Ten of the address bits are inverted on one card - F2 - which is a type 3132 card. It is a very simple card indeed, using five SLT modules. The 479 module has dual inverters, thus the five modules provide for ten signals to be inverted. 

The module used on the 3132 card

This module only requires +3V, not using the -3V bias and +6V pullup rails. The card still implements three tantalum capacitors to filter the rails, for some reason. Each of the ten inverted address bits 6 to 15 are routed to one of the inverters and the output goes directly to an output pin. The pins 8 and 9 are connected on the card, as are pins 2 and 3, thus these inverters use the pullup to +3V for their high output state and sink current to ground (pins 4 and 10) to output a low state. 

SUPER SIMPLE BENCH TESTING SETUP

My bench setup thus requires only one +3V power supply and I can test each bit by switching the input pin between 0 and 3V, verifying that the output pin moves between 3V and 0 based on that input. If the inverter for bit 9 is not working properly, I can swap in a 479 module from one of my spare SLT cards and repair its operation.