Replaced parts in solder reflow plate, tested and modified flash on IOB6120

REPLACED BLOWN PARTS ON REFLOW PLATE

The replacement for the parts that were destroyed by the 12V passing through the wrong linear regulator have arrived and today I soldered most of them on. I applied power and was aghast to see the 12V passing right through. 

I looked into this and discovered that the ground plane of the PCB (or the via that connects a group of ground pads) had failed, thus there was no ground at the linear regulator pad vref that should be grounded. I added in a jumper to bridge the group of pads to a known good ground level, at which time I validated that the voltage rails are indeed 5V not the full 12V passing through. 

With that done, I await only the temperature sensor from Mouser before I can complete assembly. Tomorrow I will program the FPGA, assuming it wasn't killed by the overvoltage. Since the ground traces were partially disconnected I am hoping that the FPGA didn't get connected to ground and therefore survived the prior voltage tsunami. 

CHECKED ON VCCW PIN POWER ISSUE ON IOB6120

I tested continuity and resistance for this pin, reflowed the pin contact and carefully inspected the chip under the microscope. It all looked good, which suggests that either I have a chip failure or the problems are deeper than it appears. 

CHECKED COMMANDS AND ADDRESSING BETWEEN REPLACEMENT AND ORIGINAL

One of the tenets of my substitution of the 16M flash chip for the 4M chip on the design is that it be almost a direct drop in replacement. That is, the pin assignments (other than two additional address bits for the larger capacity) should be identical and the functions should compatible enough to work properly.

I pored over the data sheets for the two devices to identify all possible differences after which I could analyze their impact on the substitution. The command codes are identical, the sequences are identical, the differences are minor:

• Manufacturer ID is identical but the device code differs for the Read ID output
• VCCw can be given 12V to do a full chip erase faster, but usually gets 5V
• Two higher order address bits are added, A18 and A19

MODIFIED ADDRESS PIN WIRING FOR THE FLASH CHIP

I realized that since both chips have some low address blocks that are only 4K, intended for boot and parameter storage unlike the 32K word blocks in the bulk of the device, it is not correct to let the two high address bits match the value of adjacent address pins. Instead, these high order bits need to be logical zero, which means they should be tied to ground.

I found access to ground on nearby decoupling capacitor pads, removed the solder bridges I placed on these pins, and added jumpers to give those bits the proper value. This should allow the chip to work properly.

Jumpers to take A18 and A19 to ground

NEW TEST AFTER MODIFYING WIRING

With this change, the board again refuses to pass the memory test at SBC6120 initialization. Drat. I will have to move on to the logic analyzer probing to check things out. In the interim, I did discover that I can find the some new 29F400 chips, known to work on the board with small software modifications because they are quite similar to the 28F400 that was the basis of the original design.

I ordered the chip and removed what I had on the board now. With the ROM missing, the SBC initialization hangs in the memory test section just as before, so no progress will occur until I get the logic analyzer set up and the new flash chip installed.

Flash removed and waiting for the new chip