LOGIC ANALYZER CONNECTION TO IOB6120 MORE TWISTS AND TURNS
A clock is needed by the logic analyzer to know when to sample various signals, but the 50 pin expansion connector to the IOB6120 does NOT carry any clocking signals. The designer of that board depended on a much faster local FPGA clock to let him sample and detect the signals on the connector. I could do that and waste a lot of the limited memory space in my logic analyzer, but instead tied to the 5MHz clock on the SBC6120 CPU itself since that generates all the signals of note.
The FPGA runs at a bit over 29MHz, so I saved space in about a 6:1 ratio by finding the proper clock. It is present on pin 10 of the HD6120 microprocessor chip, which is where I snag it to wire to the logic analyzer clock input.
MY APPARATUS TO PROGRAM FLASH CHIP STILL NOT PERFECT
With the change of the RD/BY# pin and the introduction of hardware to capture the low-hi transition of that signal, I had a setup that I believed could properly control the 29F400 flash chip to write the contents of my PC based file into the first 128000 bytes of the chip.
However, I found that it sometimes stalled partway through a block of 256 bytes - the transition wasn't detected or didn't occur, thus my code hung up. In addition, when I did a dump of the first block, I still saw the first value xE2 repeated for the first two locations, with everything else pushed 'rightwards' or 'downwards' one position. This could be a flaw in the reading or a flaw in the writing - more investigation is necessary.
I will refactor the code once again. My thinking is that I am free to issue a new command sequence as long as the RD/BY# signal is high, even if I didn't see it dip low for some interval. Thus the interrupt routines for the rising edge detection can go away. I will also carefully slow down the code that dumps one block, to make sure that I am not inducing the problem by changing address lines too close to when I read the results.
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