2310 emulation write module rewritten and successfully simulated

BUS WRITE STEPS THROUGH A FEW STATES WHEN THE WRITE GATE IS ACTIVATED

Write gate signal starts a write. The erase and write heads are turned on and the drive begins sending out the 720 KHz  clock as it is writing each bit cell. This should continue for the remainder of the sector. The state machine stages are idle, preamble, sync word, data write, and postamble. 

The preamble is 250 microseconds of zero bit values written to the drive. Each bit value is recorded with one clock bit and one data bit each in a 720 nanosecond interval. Recording a bit is accomplished by reversing the flux of the write head. Thus in each clock bit interval the flux is reversed, but in the data interval it only reverses if the bit value is 1, otherwise the flux remains unaltered. 

The preamble is thus 250 us of alternating flux reversal and no flux reversal (writing zero bits). The drive synchronizes a kind of phase locked loop to the clock bits during the preamble thus it can know which pulse is a clock bit and which pulse is a data bit value of 1. The drive and the controller logic now sees clearly delineated clock and data bits, but the controller must also know which bit cell is the start of each word on the disk. 

The sync word serves this purpose. A flux reversal during the data interval signals a 1 bit and the end of the preamble. The 1130 architecture is 16 bit words, but the 2310 writes these on disk as 20 bits, the first 16 are the data and the next four are a check pattern to detect errors reading the disk. Every time a 1 data value is written in the word, a two bit counter is stepped. 

The goal is that the counter will be at zero at the end of a valid word. Thus if a word already has four, eight, twelve or sixteen bits that are 1, the four check bits are written as 0000. However, if the two bit counter is not yet zero, the drive will write a 1 bit and bump the counter until it reaches zero. Thus with three bits that are 1, the check bits are 1000. With two bits in the word that are 1, the check bits are 1100. With one bit that is 1, the check bits are 1110. 

The sync stage will write 11110 which is for a word of 0000000000000001 with the check pattern 1110 appended. Following this the controller is synchronized on the start of each word - the next bit cell is the first bit of data word 1 of the sector and the state machine moves to the data stage.

In the data stage, we collect the bit values coming from the controller into groups of 16, then absorb and validate the four check bits. This 16 bit value is written to the DRAM of the emulator and we start with the next word. A sector on the 2310 is up to 321 words long, so we loop while counting words. If the write gate is dropped by the controller (writing a short sector) then we move immediately to the final postamble stage, otherwise we move there are the count of 321 is completed.

The postamble writes more words of zero until we reach the end of the sector. Once the new sector arrives the state machine goes back to idle and waits for a new write gate signal. 

TRICKY PART IS DEALING WITH THE CHECK BITS WHICH ARE NOT STORED ON DRAM

The configuration values for the emulator are set for 16 bit words, which ignores the 4 check bits that occur after each word. In the RK-05, there are no check bits after each word so the logic of the emulator is directly based on bit and word counts for a sector. A checksum word follows all the data words on the RK-05, a different and improved error detection scheme from that of the 2310. 

I have to introduce separate action that does not step certain counters during the final four bit cells, while ensuring that the emulator doesn't stop the read or write prematurely because it thinks all the bits have arrived correctly. For example, the emulator calculates a sector as 5, 136 bit cells long, not counting preamble, sync or postamble. 

If you use the bit cell duration of 1.4 microseconds with that value, you would consider a sector complete at 7.19 milliseconds. However, we really need 8.99 milliseconds because of all the check bits. Adding in the duration of the sector pulse before the read/write begins, the time for the sync word and the 250 us of preamble, you are up almost 9.4 ms out of the nominal 10 ms duration of a sector. The postamble at the nominal rotation speed would consist of almost 460 zeroes - around 638 milliseconds. 

SIMULATION RUN AND ALL TIMINGS AND BEHAVIORS VERIFIED

l completed a version that ignores the check bits written by the disk controller logic in the 1130 system. That seemed to grab the data properly. I then added an ECC testing circuit that would turn on a ECC_error latch during the write and leave it on until the next write begins. It will be routed out to the Fault indicator on the front panel.