Designed replacement 5806223 card - device controller logic for the 1627 plotter attached to an IBM 1130

BASED ON BREADBOARDING TESTS, I DEVELOPED A COMPLETE SCHEMATIC

I tested my plan to use monostable oscillator chips to get the same behavior as IBM's AC triggered gates. IBM uses these, which emit a short pulse at the falling edge of one signal as long as the enabling signal is also on. This allows IBM to interface to external devices without the challenges of metastable behavior that can occur with clocked digital electronics.'

The IBM gate emits the pulse and it turns a flipflop on or off, with no clock on the flipflop and no relationship to the 1130 system clock. In addition to its use with signals outside the 'clock domain', it is also widely used to activate flipflops in many situation inside the CPU logic. 

Its primary use on this card is to set flipflops for particular bits that were set by the user as part of their XIO Write instruction. The gate uses the bits as the enabling input, and the falling edge that activates it is from a NAND gate that turns on (goes low) when we have an XIO Write to Area 5 (the plotter) at clock step T6. 

The controller logic uses pairs of single shots in series, which emit a low signal for a fixed duration. For movement of the pen on the paper, the first SS fires for 2.5 ms when its input goes low. As its output goes low for that first SS, it sets the busy condition. The inverted (high) output of the first SS is hooked to the second SS, so that when the first SS time period expires, the output goes low and triggers the second SS for another 2.5 ms. 

As the second SS goes low, it triggers an AC gate to reset the that held the pen motion bits. The low state of the second SS also drives the busy status of the plotter. When the second SS interval expires, the busy condition goes off; the falling edge triggers another AC gate to turn on a flipflop called Response. When Response is on, it drives a request for an interrupt on level 3. 

As you can see, the design depends very heavily on these falling edge detecting gates. I know that the monostable oscillator (single shot) chips have multiple control inputs one of which can act as an enable. Thus, using the 74LS122 with the B bit as the enable and the NAND gate for the XIO write as the trigger will produce a pulse in the range of 30-35ns if enable is high when the trigger edge drops. 

I also made use of 74LS74 flipflops but not in the clocked style they are normally used. I used the asynchronous set input to turn them on when my 74LS122 produces its pulse, and use the async clear input to turn them off when the second SS expires. This takes up more real estate than modern combinatorial gates and flipflops, but it behaves as the IBM circuit does. There is a NAND gate for the XIO Write, a 74LS122 to act as the AC trigger gate, and a 74LS74 flipflop that is set by the pulse from the trigger. 

FAIRLY DENSE BOARD - 22 INTEGRATE CIRCUITS PLUS PASSIVE COMPONENTS

Surface mount chips give me two flipflops per package and four NAND gates per component, but 74LS122 is its own chip. Overall I need ten chips for the single shots, plus four chips for the flipflops. The remainder are the gates that detect when an XIO Sense DSW is issued to feed the appropriate status bits, to detect the XIO Write when we are commanded to move the plotter, and all the other functions. 

The movement commands set for flipflops for up, down, left and right. These use the pair of SS with 2.5ms timing. In addition, the programmer can raise the pen off the paper or lower it down. Those operations take two more flipflops and their own pair of SS since they require 50ms per SS due to the slower mechanical motion. The four SS with fixed times (2.5 or 50ms) require an external resistor and capacitor for each to determine the timing. The SS acting as AC gates operate without external components. 

The 1627 is driven by a 12V signal that is normally high, but pulled to ground for the 2.5 or 50ms of the first SS in a pair. This trips circuitry inside the 1627 to advance the stepper motors one position. This board has open collector gates to drive those signals, with pullup resistors hooked to the 12V power rail. The outputs to the IBM 1130 are inverted logic signals -Req IL3, -DSW Bit 0, -DSW Bit 14 and -DSW Bit 15. These are pulled low by open collector gates on this board. The pullup is done in the 1130 not on this card so no resistors are needed for those outputs.

The design checks for a powered up plotter by sensing the -24V supply from the device. This is hooked to a resistor voltage divider with the upper end hooked to +12V. Thus, the condition being sensed is either 12V if the plotter is turned off or a negative voltage if it is turned on. Modern gates don't like such voltages, so I whipped up a circuit that produces either 5V or barely negative. Using a diode and current limiting resistance ensure that the gate sensing this won't be damaged by the presented voltages on its input. 

Finally, the 5V logic chips on the board are powered by a LVDO voltage regulator that drops the 12V input on the card down to the 5V we require. 

MECHANICAL CONNECTION - SACRIFICIAL DOUBLE WIDE SLT CARD

The double wide SLT card is 3" high and 3.25" wide, with its twin 2x12 sockets that plug into the backplane. My PCB is a bit smaller and will mount atop a card that has been cleared of components and readied for attachment. Small jumpers are soldered to the PCB and the connectors of the board. 

FINALIZING THE PCB LAYOUT WHILE I BREADBOARD AND TEST THE DESIGN

I am mostly done laying out the PCB with the circuitry. When I am comfortable that it will work properly I will send it out to the fab to make five boards. During the wait I will buy all the SOIC-14 sized ICs and other components to solder on the board. 

I will continue to put together DIP sized chips to verify each part of the design before committing to build the cards, using my breadboard testing gear and monitoring timing on the scope.