Testing my new seek logic for the Virtual 2315 Cartridge Facility - part 5

BETTER LOGIC ANALYZER RECORDINGS AND THEIR RESULTS

I recorded several seek movements - 1, 2, 3 and 193 cylinder movements. What I observed in all of these are glitches or spurious changes of +Access Ready which caused the 1130 disk controller to malfunction. 

For example, here I zoomed in on +Access Ready, the second signal in the trace, dropping low for a short (invalid) period which triggers the disk controller to step the count register and in this case to switch from 10 mil to 20 mil steps. It also confused the controller into turning off its =Access Go request but it turned it back on because +Access Ready was back on. 

An even more flakey case is captured on an attempted seek of 3 cylinders, which actually moved the arm just one step. The count stuttered very rapidly and reached a full count condition that stopped the seek. The drive saw only the single -Access Go with -10 Mil Step asserted, thus it moved only one cylinder. 

The arm physically moved to cylinder 175 when we requested the seek of 193 cylinders, because the count was being updated by +Access Ready glitches. 

The root cause is incorrect +Access Ready signals as seen by the 1130 disk controller. These are also being seen by the FPGA logic in the V2315CF which causes it to miscount in its own way. The state machine behind the seek shadowing function expects +Access Ready to drop 5 milliseconds after -Access Go is set low, for +Access Ready to stay low for another 10 ms and then return solidly to high. The glitches cause the state machine to advance when it shouldn't or fail to advance. 

NEW VERSION OF 2310 INTERFACE BOARD PCB ORDERED TO HELP WITH THIS

The new version has the electronic switch circuits that will directly route the +Access Ready signal coming from the disk drive out to the disk controller logic, so that it does not have to pass through the FPGA at all. The FPGA is able to see that signal from the disk drive, so that it can shadow the arm movements properly. 

I also switched the terminator resistors on the V2315CF to better match the impedance of the 1130 cables and ribbon cables between V2315CF and the 2310 Interface Board. Hopefully these will help with reflections and other signal issues for +Access Ready. 

CHANGE TO FPGA LOGIC TO AVOID THE ACCESS READY GLITCH ISSUES

In virtual mode, the V2315CF generates the +Access Ready signal using timers so that it conforms exactly to how the disk drive should work. It drops 5 ms after a seek begins and returns to high a further 10 ms beyond that. This worked perfectly in testing.

I will send that same generated +Access Ready to the disk controller logic, not the signal coming from the disk drive, so that real mode will not have the improper feedback to trip up the operation of the disk controller logic. 

My shadowing logic must be made bulletproof even with odd behavior of the detected +Access Ready signal, so that it too counts properly. I will drive it off the same timers that generate the signal for virtual mode. If we receive an -Access Go, we will step through the timing without regard to the feedback signal coming from the disk drive. I may test the state of +Access Ready in order to detect failures of the disk drive, but it must be a soft enough check that the glitches won't bother it.