WRITE STEADILY COMMANDED AS VIRTUAL 2315 CARTRIDGE FACILITY BECOMES READY
After I enabled my logic to begin testing the write functionality, because my FPGA logic had a temporary block on it, the WR indicator on the main box of the Virtual 2315 Cartridge Facility (V2315CF) lit up steadily. That stopped the FPGA from properly processing read or seek functions.
I spent some time verifying that the signals were routed properly from the cable in the 1130 disk controller through the 2310 Interface Board and the main unit of the V2315CF. I checked the routing in the boxes and the termination resistors. Eventually I determined that the signal was incorrectly generated by the 1130 disk controller logic and was not a fault in my project.
COMPLEX LOGIC RELATED TO WRITE SIGNAL
The -Write Gate signal is produced by combining the +Write Select signal with the 90 second timer that allows the disk drive to fully purge dust before it loads the heads and becomes ready. It asserts the +File Ready signal to indicate that the 1130 can use the drive.
As soon as +File Ready went on, the -Write Gate was turned on (logic low) and began driving the V2315CF to perform a write. It was due to the +Write Select going high and the source page of the Automated Logic Diagrams for this is complex, with several interlocking flipflops. The gates involved and signals are spread around on the page making it hard to understand how it all works.
In order to understand it during any debugging, I pulled the page apart and reorganized the gates so that the logic behind each flipflop and latch was easy to understand. The first issue I discovered was right at the last bit of circuitry, the Write Select Latch that generates the +Write Select signal.
WRITE SELECT LATCH SIGNALS ARE SEEMINGLY CONTRADICTORY
This is a classic latch as used by IBM in that error, formed by wiring together combinatorial gates in a loop. In this case, a NAND, an OR and a NOT gate form the latch, with the loop indicated in the picture above with the green highlighting. The OR gate is how the latch is set; the upper NAND gate will set the latch through the OR gate when both of the upper flipflops (R-W Op and R-W Select) are set. The lower NAND gate is how the latch is reset. This happens when either -DC Reset 3 or -Four Sector Pulses go low.
The -DC Reset 3 is asserted low when the machine powers up and any time the 1130 RESET button is pushed. As the 2315 disk cartridge rotates in the disk drive, four 165 microsecond pulses are produced per rotation, one each 10 milliseconds or 1/4 turn, at the start of each sector. The -Four Sector Pulses signal goes low to form the sector pulses. That resets the latch at the start of the sector marker pulse since we don't want to continue writing when we get to the end of a sector.
I put the oscilloscope on the +Write Select signal and the -Write Select Latch signal, the first produced by a NOT gate from the second signal. What I found was that both signals were the same but that could be because there is no pullup resistor on the signal line. IBM's Solid Logic Technology (SLT), used in the 1130, is a form of Diode-Transistor-Logic which is insensitive to a voltage for the high logic level, nominally 3V.
All that matters to activate a gate is that a current is sunk by the driver circuit from the input line. As long as the voltage on the input side is low enough that the diode in the input conducts, and the current that can be sunk by the driver at that voltage is high enough, it triggers the SLT gate.
Looking at the driver side of the diode in the SLT gate, when the conditions are not right for the diode to conduct, might show no voltage at all. A pullup resistor on the driver gate may establish the nominal 3V high level, but without a pullup it could show as 0. Unless we can measure the current flow into the driver gate, we can't tell if it is conducting or not.
The signals were not as they should be, perhaps due to this oddity of SLT logic. If the latch is indeed on, I need to figure out which of the two flipflops that activate it is turned on and causing the latch to set. That is, the R-W Op or the R-W Select would have to be turned on to cause the Write Select Latch to be set.
This presents some difficulties because there is no pin assigned to either of those flipflops. The only way to observe the flipflop state would be a test point on the edge of the card, something very difficult to attach to. However, I might be able to infer which is active if I can see that the signals which activate the flipflop are in the correct configuration.
R-W OP FLIPFLOP LOGIC STUDIED
The flipflop is turned on if the 1130 is executing an XIO instruction requesting a disk write, turned off either when the 1130 is executing an XIO requesting a disk read or when -File Reset is asserted. For either the XIO read or XIO write, as part of the execution the disk controller issues a short pulse to load the memory address for the data using the -File Load SP pulse. At the end of processing either a read or write, the disk controller asserts the -File Reset low.
Thus I have to monitor the four signals that would activate the flipflop. If the flipflop itself is defective and not turned on by its input signals, I would not see it unless I can somehow connect to the testpoints.
R-W SELECT FLIPFLOP LOGIC STUDIED
I can't directly see the state of this flipflop either but most of the inputs that wouuld activate or reset the flipflop are accessible; unfortunately the R-W Op flipflop is one of the sources, which I explained in the section above is difficult to observe. The R-W Select flipflop is turned off either from the -DC Reset 3 system wide reset signal or when read or write completes by asserting the -Int Req Lvl 2 to raise an interrupt to the 1130.
Setting the R-W Select flipflop occurs only when the sector marker pulse begins at the start of one of the four sectors on the disk. Another flipflop, R-W Req, must be on. If the sector number that the XIO instruction requested matches the sector that is just about to start (+Sector Equal) and the disk arm is settled, either the top or bottom NAND gate is active, based on the state of the R-W Op flipflop. That active NAND will turn on the R-W Select when the sector marker pulse begins.
The overall logic is that the XIO instruction for read or write will set the R-W Req and because the type of data transfer is indicated by the R-W Op flipflop, the R-W Select turns on right at the start of the correct sector that the instruction has requested. The request (R-W Req) could be active for a majority of a disk rotation until the target sector arrives. Finally, the write select latch is set when the R-W Op flipflop indicates that a write was requested and the R-W Select flipflop turns on because we are at the correct sector to do the write.
R-W REQ FLIPFLOP LOGIC STUDIED
The R-W Req flipflop is set when the -File Load SP pulse occurs during the XIO instruction execution, when it is either a read or a write XIO. It is turned off when the data transfer completes and -File Reset is asserted, or when the R-W Select turns off because we hit the next sector marker while still processing the read or write. I can monitor the R-W Req flipflop state as well as the R-W Select and other signals that drive the R-W Req flipflop state.
READ CHECK FLIPFLOP LOGIC STUDIED
There is one final flipflop on the ALD page, but it is only involved with an XIO read instruction. One can set bit 8 in the control field for the XIO Read instruction to request that it does not transfer the data, it just reads the disk. This validates that the sector has valid error correction bits otherwise the drive will flag the error.
When the -File Load SP activates during the XIO instruction execution, if bit 8 of the control word was on, Read Check flipflop is turned on. If it is a write rather than a read, then this is ignored, which is why they don't involve the XIO write signal. The flipflop is turned off either when the -Int Req Lvl 2 turns on or the -File Reset signal is turned on at the end of the operation. I won't need to debug this flipflop.
NEXT SESSION I WILL DEBUG THE SIGNALS ABOVE TO FIND THE FAILURE
When I get to the shop on Tuesday I will check all the signal sources and behavior of the circuits studied in this post. I will report on the results in the next blog post.
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