Testing Virtual 2315 Cartridge Facility capturing data written from the IBM 1130 to the virtual disk

RAN WITH THE NEW LOGIC, TESTING WRITE IN VIRTUAL MODE

Armed with the logic analyzer trace of the exact timing that the Virtual 2315 Cartridge Facility (V2315CF) would see of the two related signals, -Write Clock Phase B and -Write Clock and Data that are used during a write to the disk, I arranged the logic in the FPGA to capture the correct bit values so that they could update the sector data in the RAM, just as the sector would be updated on a 2315 cartridge in the internal disk drive of the IBM 1130 if we had not installed the V2315CF to intercept the signals. 

The method used to store data on the internal disk drive (2310) uses two 690 nanosecond long intervals, back to back, to record each bit. The first of the two intervals always has a pulse, which is a clock. The second of the two intervals only contains a pulse if the bit value is 1, otherwise the interval passes without a pulse. 

A sector begins with a long string of 0 bits, allowing the drive to synchronize in order to assign each pulse it sees to either a clock or a data signal line. The first 1 bit defines the start of an 1130 data word begins as the next pair of intervals. The 1130 has words of 16 bits, but on the disk an additional four bits are recorded for error checking. Thus there are twenty pairs of intervals per word, with up to 321 of these fitting on a sector of the disk. 

When a write begins, triggered by the 1130 activating the signal -Write Gate, the disk drive starts generating a clock signal of 1.44 MHz while which is assigned to be the clock, then on the other half of the cycle it will only emit a pulse if the data bit value is a 1. Both the clock and the data interval are s nt on the same signal line -Write Data and Clock, which the V2315CF has to evaluate to determine which bits are a 1 and which are a 0. 

When the -Write Clock Phase B signal drops from high to low, which marks the data interval, my logic will grab the value of -Write Data and Clock and if it is low, the bit value is a 1 otherwise if high the bit is a 0. It had previously waited through the initial sequence of 0 bit values until the first 1 bit is seen. We then collect the next 20 bits and save the first 16 as the word. 

The last four are a special pattern that matches the number of 1 bits in the first 16. This error checking code allows the disk drive to detect errors when reading back the data later; if the error checking bits aren't write, the 1130 flags the data has invalid. 

RESULTS OF WRITING A SECTOR TO THE V2315CF WITH THE NEW LOGIC

I started up the 1130 with the V2315CF in the virtual mode. A mini 2315 cartridge was inserted into the V2315CF and loaded, so that the File Ready light illuminated on the 1130 console. I executed an XIO Start Read instruction which brought the data from the sector into memory. I altered a couple of words of the data and then issued an XIO Start Write to put back the modified data in the sector. 

I zeroed out the area of memory then repeated an XIO Start Read to bring back the value from the V2315CF into memory. If it matches the modified version and as long as the V2315CF validates that each word had the correct error checking code when it was written, then we know that the write is working properly. 

However, initially I was getting garbage in the buffer and back on the mini cartridge after I unloaded it. I traced it down to an error that regressed into the code as I was adding in some diagnostic output. The memory controller was not properly advancing the address after writing each word to RAM. It took a while to find it, some simulation to prove it however the fix was quick. I just returned the proper logic statement to the code and that issue was gone.

However, I was back to the problem that the logic was not capturing the bit stream coming from the 1130 system. I put the logic analyzer on to the V2315CF and captured four signals: 

• -Write Gate (which turns on a write to a sector)

• -Write Clock Phase B (the clock signal I send to the 1130 to cause it to emit both clock and data bits depending on whether this signal is high or low)

• -Write Clock and Data (a value of 1 that is either a clock bit or a 1 in the data. A 0 data value is sent as a zero during the data portion of the prior signal)

• Bit value (a diagnostic output set to 1 when the data bit value of 1 is detected). 

I saw that the logic did NOT identify the start of the data on the sector, which would be a specific bit pattern that is the sync word. The capture during the time when the 1130 is sending the sync word is below. The four signals above are shown in order as horizontal traces. 

The sector begins with a long string of 0 data bits which is terminated by the bit sequence 1 1 1 1 0 causing the logic to begin sending 1130 data words as streams of 16 data bits plus four error checking code digits. The sync word is a word of value 1000000000000000 plus an ECC sequence of 1110 that validates the word as properly formatted. At the end of the sync word, the next bit is the start of the first data word of the sector. 

The -Write Clock Phase B signal alternates strictly at a 720 KHz rate, with the high level denoting the data portion of a bit cell and the low level of this signal signifying the clock portion. During the clock portion of every bit cell, the value of -Write Clock.  and Data is a logic low which means a 1 bit for the clock. There is always a clock bit in every bit cell but during the data portion of the bit cell we either have a logic low on -Write Clock and Data which means the data bit is 1, or a logic high that means the data bit value is 0. It can be confusing to interpret because of the inverted logic - a logic low means a value of 1.

The failure to detect the sync word is visible because the fourth signal in the trace should emit a 1 for each bit position that is transmitted as a 1, but it is a while later before the logic begins emitting that signal. This means it did NOT detect the sync word properly. 

At least I now have a view of the data coming in from the 1130 which should help me devise a strategy for reliably detecting the bit values. A bit of design work, some extensive simulation and then I resume testing in the workshop.