The cause of my 'off by one' retrieval of RAM was elusive, requiring quite a few different diagnostic cycles and tests before I finally went to the output of the memory access itself. I was getting consistent trash returned that corresponded to the junk returned by my USB logic.
This might stem from setup and hold times for the memory address, or some other RAM signal defect. Why this only happens on the first pass reading is part of the mystery. I changed the focus of my testing and continued on.
Too, I tightened up how I set and held the address for RAM, not only for reading but also when originally writing. When an FSM is triggered in part by what state another FSM has reached, there is an unavoidable one cycle delay, since it is really reacting to the state the FSM was in at the end of the prior cycle. This can lead to timing issues if not careful.
The logic analyzer shows me the wrong contents coming out of RAM for location zero, but also shows me what appears to be the correct words being written in. The wrong data is consistent. To check whether this is an issue with the address going to absolute zero, which is cyl 0 sector 0, I set the sector to 1, did a read, and saw the exact same pattern beginning at location 0x040000 which is where cyl 0 sec 1 begins.
I restructured my 'read field(record)' FSM a bit to hold addresses longer and more consistently, hoping that might help resolve this flakiness in what was written. Still no change. The logic analyzer shows the data bus as zero and the RAM address as 0, when I write the first word to memory.
However, when I retrieve the first word, I get 0313 coming out in the first cycle, when it is latched, and then a few more bits turn on and stay steady for subsequent cycles. Nothing is writing to the bus, as far as I can tell, other than the RAM chip.
More changes, further protecting the duration of signals and experiments to see if the problem will go away. So far, the failure is consistent and the cause unknown.