Wednesday, October 12, 2016

Working carefully through entire read sector using logic analyser

Today I spent time with the rest of the 1401 Restoration Team at CHM.


I have begun a methodical check of the entire process, the 40ms in the life of a read sector transaction. For each step, I will set up the logic analyzer to verify that things occur as I expect them to. For example, I need to verify that my 'got sector' is emitted for the correct sector number, not just that I get that signal during a rotation.

The steps that will occur and must be verified:
  1. Readsector logic is waiting for a sector match
  2. Indexmarker occurs, signalling that next sector mark is for sector 0
  3. Sectormark occurs, thus we are in sector 0 now
  4. Gotsector is emitted to indicate we have a match
  5. Readsector logic moves on to setup for record 1 of the sector
  6. Readfield logic is triggered
  7. Readfield waits for approximate 200 us preamble before looking at incoming data
  8. Roughly 120 us of zero data bits are seen
  9. A 1 data bit completes the sync word
  10. the logic recognizes the synced state
  11. Two words of the header record are deserialized, extracted and saved
  12. The checksum is calculated correctly for the two words of the header record
  13. The next word is deserialized, extracted and used as a checksum
  14. The checksum verification test occurs properly
  15. The readfield logic completes
  16. The deserializer goes to the unsynchronized state
  17. The readfield logic for the next record, label, begins
  18. The appropriate preamble is passed before we look for sync
  19. Enough zero bits are read to properly set up sync logic
  20. A 1 bit is read and the sync condition is attained
  21. Eight words of the label record are deserialized, extracted and saved
  22. The checksum is properly calculated for the 8 label words
  23. The next word is deserialized, extracted and used as a checksum
  24. The checksum verification test is done correctly
  25. The readfield logic ends
  26. Sync is dropped
  27. The readfield logic is entered for the data record
  28. A suitable preamble is passed before attempting sync
  29. Enough zeroes are read for the sync engine to work properly
  30. A 1 bit arrives and we attain the sync condition
  31. 256 words are deserialized, extracted and saved as the data record
  32. The checksum is properly calculated
  33. The next word is deserialized, extracted and saved as the checksum
  34. The final checksum test is done properly
  35. Readfield logic ends
  36. Sync is dropped
  37. The readsector logic completes
  38. Appropriate completion status is set in Reg0001
  39. The next sectormark does not occur until after step 36
Each set of testing and each tweaking of logic takes about 30 minutes through the toolchain. In some cases, the 4K cycles of a logic analyzer capture, accounting for about 204 us, will let me check off multiple steps. The entire trace buffer is less than 22 words of deserialized data, and preamble and sync times account for multiple word times as well. 

Thus, we might view the entire header record in one shot, but the label record may take two capture intervals. The data record, needing almost 270 word times of data, either needs a dozen captures or some faith that allows capture of just the beginning and end. 

By the time I left for the CHM, I had verified steps 1 to 4 of the list and was attempting to work through the looooong preamble before the header record. I see that we are good through part of step 7, in that I see spurious data bits arriving in the first 30 us of the sector, and they are indeed being ignored because we are still in the preamble state. 

I set the logic analyzer to wait 4032 fpga clock cycles after the sector mark occurs, then watch for the synchronizing behavior. This is the preamble duration of the Alto microcode, 21 word times.  I am seeing the sync bit arrive just about where expected. Further, the collected data from the disk does appear to match the two header words I would expect, with 0000 0000 from sector 0.

The scope pattern is consistent with the checksum I would expect, 0141 in hex, but I don't yet have a good logic analyzer signal to validate the checksum testing results. That will be the last set of tests for tonight. I am comfortable that steps 1 to 11 are verified and probably that the next couple are good, but time will tell. 

I made a one line change to route a different signal to an LED and the logic to match sectors stopped working, such that my logic analyzer trigger no longer was recording. I suspect this is one of those random Xilinx abject failure modes where some other set of trivial and unrelated changes will result in a bitstream that once again works properly. Time to sleep, since progress for tonight is blocked. 

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