I set in to the wiring of the 3.3V fpga signal lines to all the level shifters. By lunchtime I had 7 of the 27 wires run. When I got back from some chores in the midafternoon, I went back to working on the board. In addition, I worked through my WriteField and WriteSector logic, to begin testing the writing/updating functionality of the tool.
I will initially test the write functions with the WriteGate and EraseGate held in the off condition, so that I can watch the flux reversals being emitted without committing them to disk until I am satisfied. This required a big revamp of the logic analyzer signal assignments and trigger conditions.
By 3PM, all 12 of the input signals were wired to the fpga and the 'personality' signals, Sense20 and Sense22, were grounded to indicate that this is the Alto style driver role board, distinct from the oddball format driver role board I built around an existing cable, and distinct from the disk emulator role board.
I have 15 more 3.3V lines to wire, for the outputs from the fpga, then I can test the board carefully. I have been checking for shorts to adjacent pins on the relatively high density FX2 and IDC 40 connectors, but also on the all component connections.
Next up would be power, ground and other shorting tests. If the board seems good, I hook it up to power and test by driving various input and output lines to see that the corresponding side responds appropriate.
There will be some logic changes for the fpga, since this board has sector number data but no index marker pulses, thus I bypass my counting circuit and use the Diablo derived sector number. Those changes were made, but will have to wait until the board is ready before being tested.
I hooked up the scope to the testpoints on the disk drive board in order to test the current timings before I make any changes to the drive. I saw a nice clean pulse on TP3 but the one coming from TP5 was ugly - ringing and jitter. Timing was very hard to read but I thought I had finally figured it out.
I removed the two fixed resistors, inserted potentiometers in their place, and tried to adjust the timing properly. I found the scope display so obscure I am not sure whether I got it right. The test point is a mixture of three signals, two of them the 440 and 460 pulses. They are switched based on whether the prior bit was a 1 or a 0, to compensate for bit shift.
I saw all three signals, jumping around, and was just not sure that I saw the long time (460 ns) edge. Thus, I feel decent about the short time, 440 ns, but far less so for the other one. I am not ready to use the drive and need to get the timing more exactly adjusted.
As a consequence, I am going to add micrograbbers to the output pins of the two timing circuits, that generate the 440 and the 460 ns intervals, to directly observe them. I will either see the pulse or not, depending on whether a 1 bit or 0 bit was seen, but when it fires it will always be one duration.
With the better scope points, I was easily able to distinguish and adjust the two timers to dead on the 440 ns and 460 ns targets. I then measured the potentiometers to determine that I need a 144.5K and a 53.1K fixed resistor to make the drive run with these timings. I am off to Anchor Electronics in the morning to pick them up.
In the early evening, I printed out the WriteField, ReadField, WriteSector and ReadSector FSMs in order to apply the learnings from the read functions to my write logic. I also worked on the board a bit more, wiring up 4 of the 15 output signals from the fpga.