I began the morning with a careful wiring check of the new level shifter/driver board, ensuring no solder bridges, all signals wired correctly and that outputs corresponded to the intended inputs. With that done, it was time to set up the testbed.
My tests with the drive switched off looked good - I saw the signals pulled nice and low, with decent speed edges. As a safety measure, I am going to check the critical signals - Write Gate and Write Data plus Clock, as these must absolutely remain high to protect the disk cartridge from inadvertent writing/erasure.
Once that was confirmed, it was time to spin up the disk, try some seeks and attempt to read a sector. The seeks appeared to work perfectly, including errors if I attempted an invalid cylinder, one above 202.
An afternoon test will check to verify the positioner indicator on the drive against the cylinder I attempted, to test that all the address bits work and are in the proper position. I found that cylinder bits 64 and 128 were swapped, which was easy to correct in the fpga logic, otherwise seeking works exactly as desired.
The read test results were mixed. It appears to read sector 0 of each cylinder, although I have yet to validate the data recorded by the logic. If I select any non-zero sector number, it hangs, indicating that my logic to count sector numbers and match is going awry.
My late afternoon testing session would monitor the Read Data and Read Clock signals, as well as the sector marker and index marker inputs, to be sure they were being read properly. I will use the oscilloscope for this task.
The Read Data and Read Clock signals looked good. I am less sure about the sector and index marks This will be tested more completely tomorrow
I will also hook the logic analyzer back to the fpga board, so that I can record what the logic believes is being decoded and stored, comparing it to what is written to the file and sanity-testing it against what is likely to be on the real disk sector.