Wrap up virtual 2501 card reader support for SAC Interface Box
I cleaned up the logic in the Python programming for handling the 'hopper empty' condition. I will do some testing this morning to validate the operation of this, after which I need to wrap up my virtual 2501 card reader testing.
I open and read in a PC file in either IBM 1130 simulator 029 or binary format, buffering it in memory and maintaining a count of the number of card images. When the buffer drops to just one card image, it corresponds to a card sitting in the pre-read station of the physical 2501 reader.
As soon as the hopper empties on the real machine, the card reader drops out of Ready. This allows more cards to be placed in the hopper, the Start button pushed and the reader return to ready status to read more cards. . I handle the adding of cards by processing the next file and appending it to the buffer in my program.
If the card deck was complete when the 2501 reader goes to not ready state, then pushing the Start button without adding cards to the hopper turns it back to Ready in a special condition called "last card". The next XIO Init Read command will fetch that card image but have the last card bit turned on in the DSW. This is how the programming can tell that the last card was read.
Thus, when a finish up an XIO Init Read command in my virtual adapter, I check the count of remaining card images. If the count is now 1 but my 'last card' checkbox is off, I set the virtual reader to "Not Ready" and update the DSW to indicate this. If, on the other hand, the last card checkbox is on when we reach a single card remaining in the buffer, I leave the reader in "Ready" state. If the buffer has no cards left, then we had been in 'last card' state and I add in the last card bit to the DSW as this XIO Init Read completes.
I used a few small decks to check this out. The behavior should be that the reader is Not Ready if there is only one card left in the hopper (buffer) with last card unset, or Not ready with zero cards if we had last card set. Adding a file when the buffer has one card, last card is unset, and the reader is Not Ready should update the card image count and turn on Ready due to the additional card images.
I set up for testing and results were fairly good. I still have some vagaries in behavior to deal with. I ran out of testing time in the morning due to another obligation, but was able to resume later in the afternoon.
I am not seeing consistent updating of the DSW nor consistent resetting of the last XIO function. It wasn't immediately clear where this is malfunctioning. I have to ponder the way the transactional mechanism is working and figure ways to record the progress. This appears to be a good time to haul out the logic analyzer - the small one based on a small fpga board I own, and start tracking the progression of the various transactions to spot what is wrong.
High speed SPI link test preparation
I built most of the logic to go in the Nexys2 board which will be the fan-out slave that gives me many more input-output pins in order to hook to all my peripherals. This board has an SPI slave module and complementary logic to the data pump I built in the main fpga board. Its purpose is to send out signals from the eight slide switches and four pushbuttons, which the initial code in the main board will echo back. The slave board takes the input lines and uses them to drive the eight LEDs and four seven-segment displays.
I set up for testing and results were fairly good. I still have some vagaries in behavior to deal with. I ran out of testing time in the morning due to another obligation, but was able to resume later in the afternoon.
I am not seeing consistent updating of the DSW nor consistent resetting of the last XIO function. It wasn't immediately clear where this is malfunctioning. I have to ponder the way the transactional mechanism is working and figure ways to record the progress. This appears to be a good time to haul out the logic analyzer - the small one based on a small fpga board I own, and start tracking the progression of the various transactions to spot what is wrong.
High speed SPI link test preparation
I built most of the logic to go in the Nexys2 board which will be the fan-out slave that gives me many more input-output pins in order to hook to all my peripherals. This board has an SPI slave module and complementary logic to the data pump I built in the main fpga board. Its purpose is to send out signals from the eight slide switches and four pushbuttons, which the initial code in the main board will echo back. The slave board takes the input lines and uses them to drive the eight LEDs and four seven-segment displays.
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