Beginning testing of virtual 2501 card reader through SAC Interface Box

SAC INTERFACE FOR ADDING PERIPHERALS TO THE 1130

I completed coding the virtual 2501 logic at both ends - python program on PC and VHDL for the fpga board. I uncovered one design challenge for the protocol to handle a virtual device, which I needed to sort out and then adjust the codes appropriately.

The issue is the sense DSW bits, which include the completion bit that should be reset by a Sense DSW with an appropriate modifier bit. However, the virtual adapter code in the PC does not participate in a Sense DSW function, so it has no way of knowing that the condition is to be reset.

The solution will require some addition bits in the UCW which will communicate when a reset has occurred in a Sense DSW, thus turning off the condition in the PC side adapter. For timing reasons, switching off the interrupt request and the bit in the UCW that drives interrupts should be handled by the fpga code.

The PC program polls for commands, which introduces long and variable delays in checking the UCW, yet the software in the 1130 has every reason to expect that once it executes an XIO Sense Device with a reset modifier bit, the interrupt request will be off. Immediately after the Sense Device, the program can return from the interrupt handler and it should NOT trigger another interrupt due to pokey handling of the reset.

Thus, I need the UCW bit that triggers interrupts handled locally in the fpga but I also need the adapter logic to see that the reset has occurred. The bit can't be solely controlled by the fpga, therefore, but also by the adapter logic running in the PC.

I had three spare UCW bits which I have now assigned to represent up to three interrupt levels that an individual device can use, thus each of the three can be reset by the associated bit in the XIO Sense Device modifier field. I defined a new transaction type, code 13, which fetches and clears the three new bits in the UCW. Thus, each virtual device adapter in the PC can grab any reset conditions, update their shadowing of the state in the DSW and act appropriately. The UCW bit for interrupts will be driven by one of these new bits, allowing for an immediately clearing of the interrupt.

I still had a window of vulnerability, when the device has set a bit such as Operation Complete in the DSW, sent that down to the UCW, which then causes my interrupt level to be set into the new UCW bits. When they are cleared by a Sense DSW w/reset, the operations complete bit remains in the DSW and may be fetched by subsequent Sense DSW commands up until the point that the PC program polls the new bits and sends down an updated DSW. On a physical adapter, the Operation Complete bit would disappear at the time of the Sense DSW w/reset, not later.

To solve this, I set the UCW DSW bit for operations complete based on the state in the fpga - flipped on when the PC side program sends a DSW with this bit set, turned off by the Sense DSW reset command. The Op Complete from the PC is only used to trigger on the Op Complete bit maintained in the fpga.

My testing began, but my polling routine was never seeing the XIO Init Write function codes in its polling loop. This called for instrumentation of lights on the SAC Interface Box to show me whether I was setting the UCW function bits and even seeing the XIO command.

After resolving a dopey mistake I had made in the test program setup, I got back to the testing. My remaining time before dusk was limited so I didn't make much progress but could do more logic development inside at night.