Tuesday, May 12, 2015

Very little time to work on the 1130 until today

The holiday weekend (Mothers Day in the US) took up almost all my time, plus I had to attend to other obligations on Monday, thus progress was at a standstill until I could get back to things by Tuesday.


The root of the odd behaviors I see stem from a few causes, as I spotted using my small fpga based logic analyzer. Mostly, these are challenges causing all the FSMs to come out of reset in a controlled way - in some cases needing an extra startup cycle to allow the input signals to reach their proper initial states. One of the fixes I implemented was to convert most of the FSMs to implement synchronous reset, rather than asynchronous reset flipflops, then worked out the right sequencing for startup.

It took far too long to get the logic analyzer going. First, when I hauled out one larger unit I had, I couldn't find where I had stashed the pods that connect the signals into the unit. I spent quite a bit of time searching and moving things around in storage sheds.

Then, when I decided to use my Spartan 3 fpga board based logic analyzer, I found that the client program on the PC no longer worked. It was an old bit of Java code that was way too dependent on Java releases and a funky serial port library.

I had to locate and install a substitute client program to communicate with the fpga, set triggers and display the recorded signals. Finally by late today I started recording groups of signals to watch how the core processes were working. Each discovery means a change to the main fpga logic, perhaps some changed signals for the logic analyzer, then setting up for a retest.

I am back on the hunt for any remaining issues with the SAC Interface Box. I hope to be moving forward at a better pace in the coming days.

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