Thursday, May 14, 2015

Very good progress on the QA of the SAC Interface Box core functions


When I pushed high volumes of data to store in core memory, sporadically it would get out of sync and the data would not be in the proper address. I finally traced it down to the behavior of the USB module interface, which could sometimes give me two words in sequential cycles and other times have a delay between the words, but mostly the delays occurred.

Since the two consecutive words were rare, I hadn't found them in any logic analyzer recordings. This meant I didn't know how it would behave, the documentation mainly consisted of a couple of sample fpga demonstrations which were designed around high speed streaming. My logic didn't handle the consecutive case properly, but now it does.

I loaded the disk initialization utility program into core and ran it to the point that it was looping trying to access the disk drive, which I kept powered down. The focus turned to the device adapter functionality.

I changed the instrumentation of the fpga to examine behavior surrounding virtual device status, XIO instruction execution and UCW status. With these done, I ran some testing and spotted a flaw in how I converted one of the FSMs during my revamp a couple of days ago. After some more cleanup, it is ready for more testing however it is also well after dark and time to quit for the night.

It shouldn't be long now until it is all working to my expectations and I can finalize the virtual card reader verification. From a development standpoint, I can finish up the data pump over high speed SPI to the slave fpga board, so that I can hook up the paper tape and plotter peripherals for their checkout. Ultimately, these will instead be handled by the medium speed SPI link to Arduinos and other controller devices, but I haven't built that link up to the point where it can be used yet. Good pr

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