Wednesday, August 31, 2016

Struggling to get RAM function working

I spent much of today at the Computer History Museum meeting with fellow 1401 restoration team members.


I did a bit more work building up the logic, creating a FSM that will stop sync, wait for a preamble duration, then wait to sync again and accumulate the desired number of words into the sector buffer beginning at the given start address. I can string several of these together to read a sector, and then that larger FSM can be invoked iteratively to read an entire cylinder.

I discovered the cause for my inability to read/write the DRAM using the existing reference logic provided by Digilent, which should work. The module uses 'inout' for the tristate memory bus but when it is used in an interior module, connected out to the memory chip pins, something goes awry.

Xilinx doesn't support internal tristates and somehow mangles the logic even though I just want to direct wire the output of the internal module to the RAM bus. I have encountered this with other logic and have had to do one of two distasteful things to deal with it.

Either I have to change the module to separate out and in buses plus a muxing signal, or I have to pull the code that uses the tristate up to my highest level module making it denser and more complex. I chose to split the bus to individual directions and add a mux signal, as I have done in other fpga projects.

This initially didn't work, but then I decided to add pullup resistors to the tristate bus pins for the DRAM. My next test showed every output as 0xFF so that isn't useful. I removed the pullup and tested again, observing the LEDs for signs of the changed data going in and coming out.

I can see that the correct data pattern is displayed on the LEDs for each byte I tried to write, but when I read I always get zeroes. There are some possibilities - the RAM is defective, something is not working right with my tristate connections, or something is wrong with the RAM code or its hookup.

The Adept utility has a different function that will configure the FPGA with a special bitstream and then read or write the same RAM memory. I used it and validated that the RAM works correctly. What does not work properly is the module I have, probably some flaw in how I have it set up or an issue with the way I handled the tristate mux.

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