Tuesday, September 6, 2016

progress on RAM access logic for disk tool

I flew to San Diego to vacation for a few days at the Del Coronado. Sitting in a poolside cabana with power, wifi and other amenities, I could concentrate on logic development and debugging through simulation.


I began working ou the scheme for the FSMs that would produce the write head signal, serializing words and encoding the bits in the non-return-to-zero methodology used on the disk. This is a scheme where reversing the state of a bit will end up creating a pulse when the sector is read. It is the timing of the reversals that produces both clock and data bits.

The driver will toggle the state of the 'write clock and data' line once each 600ns, to generate the data clock pulse on reading. Right in the middle between those clock pulses, if there is another pulse, then the bit value is 1, while the absence of a pulse means a bit value of 0.

The driver toggles the state of the line once at each 600ns point, but switches again 300 ns after that to encode 1 bits. If each bit of the line is a constant 300 ns, then the pattern of all zero data bits would be represented by 11001100110011001100 etc. The reversal of the signal line produces the clock bit, but the next time interval has no reversal so no pulse is produce. If I wanted a pattern of all one bits, the pattern might be 1010101010101010101010 etc, switching state to produce pulses each 300ns.

Synchronization is the process by which one determines which are the clock pulses and which are the data pulses. The logic sees a long stream of words with all data bits 0, which means a long string of pulses every 600ns,nothing in between them. The circuitry or logic locks timing to that pattern and recognizes the pulses as the clock bits.

Finally, after the long string of zero bits (patterns like 100110011001100110011) a data bit of 1 occurs in the 300ns position halfway between clock bits. That single bit of 1 indicates that the very next data bit will be the first bit of a word. In our pattern just above, the 10011001100110010, in its last transition, caused a toggle in the data bit position and now we are synchronized to know where to ind clock bits, data bits and the start of a word.

Writing this from my logic is easy - I have a write signal FSM that will cycle forever between four states - clock pulse activation for 100ns, quiet space for 200ns, optional data pulse or quiet time of 100ns, and quiet time of 200ns. This FSM must get the data bit value, 0 or 1, from the serializer FSM which is grabbing words from my buffer in RAM then shifting them out, one bit per cycle of the write signal FSM.

Writing involves turning on the 'write gate' signal which causes the erase head and write head to begin magnetizing the disk surface. Due to the construction of the head, the first 25 us after the write gate produces write signals but the erase head has not cleared the track yet - the erased section is 'behind' the written section by that time. The signal produced in that duration cannot be reliably read.

The solution is to ignore certain parts of the recorded signal. When writing a sector, a bunch of zeroes followed by a 1 bit is produced for some duration, but on reading, the read signal is ignored for part of that time. When the logic begins looking at read clock and data pulses, we are in the middle of the long stream of zero bits and safely past the point where the erase head hadn't worked.

Thus, we write sections of all zero bits to allow the read process to wait and reliably be in the midst of the zeroes before it starts reading. The zero bits before synchronization are called a preamble. At the end of a field, following the last (checksum) word, there are a few words of all zero bits, called a postamble.

This is important in the space between the three fields or records of a sector. For illustration, we will talk about the end of the header record and the start of the label record. The checksum word of the header record is followed by four postamble words of zero, then five preamble words of zero before the sync 1 and word 1 of the label record.

When reading the header and then the label field, this permits the logic to turn off the read gate or stop looking at the read clock and data bits right after the checksum word of the header record. The logic waits long enough to be about halfway through the four postamble plus five preamble words of zeros, then switches on reading and waits to resynchronize.

If the operation read the header record but then rewrote the label record, which is possible with Alto disks, then we are going to wait for the time of one word, to move into the postamble of zeroes that was previously written, then turn on the write gate and start toggling in zeroes to produce the 4 postamble plus 5 preamble duration of zeroes.

That way, when reading the originally written header record, then turning off the read head for part of the gap, it will find a good preamble and sync written in the update for the label record.

I found that my memory driving FSM double fired, because the read field FSM kept the trigger field active too long. Changing Read Field to drop the trigger after one cycle ensures that I will get just one memory cycle.

No comments:

Post a Comment