Friday, September 2, 2016

Debugging work on Xerox Alto II with logic analyzer, bit of work on Diablo driver/emulator

I spent most of the day away, working on the Alto restoration, but did cobble together a bit on my Diablo driver.


Today the team met to work on the Alto. We wired it up to a logic analyzer and began our debugging of the inability to boot up from disk at startup. This took quite a bit of time and involved a few complexities.

In order to capture the current address of each microinstruction being executed, we had to put a chip clamp around one of the ROM chips. That in turn required us to use a board extender to gain access, and a cable extender since the far end of the board had an active connector attached.

After cabling the ROM chip to the analyzer, we hooked to almost 70 other signals from the backplane. When we had it all set properly, we could begin capturing execution of the various microcode tasks and try to work out why the boot sequence is not working.

We found that the parity error task is invoked on the very first memory access. Further, we see that the Error latch is on when the machine starts and stays set perpetually. This should be resetting both at startup and when the parity error task ends.

What we don't know yet is whether this is a problem with the RAM boards, thus a real parity/hamming code error, or if the flaw is in the error detection logic itself. To do this, we will have to cable another 40 pins at least, to see what is going to and coming from memory. We are also trying to map out a debugging sequence where we might just scope some internal signals to check out the error detection logic.

One big unknown before we started was whether the ROM contents matched the versions for which we had listings. Debugging would have been quite hard if not, since each microinstruction branches to the next one, rather than executing sequentially in the usual fashion, so they are interleaved fairly randomly throughout the 1K words of ROM.

Ken Shirriff used a partial disassembler and some inductive logic to work out most of the ROM contents given the listings we found online. We were delighted to find that the addresses we saw matched exactly.


My male plug (MRAC 42 pin connector) arrived, which I can begin soldering up with twisted pairs for connection to the other FPGA extension board which will be used for the disk emulator role. I can't solder in both ends until I get the connector shell which has left Israel and could be in transit, in customs, or traveling across the US.

I also received by 74HTC125 chips and zener diodes to speed up the timing critical circuits, those that deal with data streaming to or from the disk heads.I still have to modify my driver extension board to put these on for the Read Data, Read Clock, and Write Data plus Clock signals.

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