Tuesday, September 6, 2016

Diablo driver logic ready to read target sectors from live disk, working on write logic


I zoomed in on the simulation signals for my RAM access FSM in order that I ensure all of them meet requirements. Some must be active and held steady for a bit before the activation clock edge (setup times). Some must maintain their state for a bit after the edge when the activation is dropped (hold time). I also checked that every signal is in its proper state.

I had a bit of tweaking of ancilliary signals but eventually I had a good solid write of the word that was assembled from the bitstream off the disk drive. Time to finish and test out the entire Read Sector FSM.

I had to set up the actual numbers for the preamble wait time before reading each of the three sector records, which I got from my notes. Then, I set the target to read sector 5 and aligned the timing of the testbench to that point.

I was able to read the header record and then sit syncing but never found the 1 bit because it wasn't in my testbench yet. I first did some tweaking of the preamble timing and verified it was right, before sticking in the sync word at the right point to continue reading my sector.

By the midafternoon, I had the read sector routine up to checking the checksum of the second record (label field) against the calculated checksum, after which it would wait for a preamble and then read the data field (record 3).

I realized that my testbench was delivering a single 1 bit to sync up, but the actual timing would be 15 zero  bits and then the 1 bit. Because of this, I am shortening the sector duration and need to expand to exactly match what should be read or written on the disk cartridge.

The outcome is that a full sector takes 3.120 milliseconds out of the 3.333 available between sector marks. That is quite reasonable.

I had a fully successful read of the entire sector 5, using accurate timing of the Read Data and Read Clock signals relative to the sector mark pulses I was generating. Proper timing, checksums match, everything seemed good.

The next verification to make was that the RAM addresses were generated properly - 00000100010101000000000 to 00000100010101100001001, which would mean that my entire read sector logic was now read to test with live data from a Diablo drive. It passed with flying colors.

Early evening, before dinner, I began building up the logic to write to the disk drive. This involves generating transitions for mixed clock and data pulses, a transition each time there is a pulse. Transition means that the bit value reverses, so a pulse could produce either a 1 or 0 depending on the immediately preceding bit value.

The timing critical routine is a state machine which turns on the write gate, waits 2 microseconds for the erase head to catch up with the position of the write head, and then begins writing a transition for a clock pulse every 600ns, with transitions halfway in between for any data bit that is 1. This routine emits a single pulse to request the next bit value when it emits the clock transition.

The higher level state machine, to write a field, will have to start the write FSM and feed it the preamble, a set number of words of all zero bits, then the data fields, write the checksum after the data and then emit three words of zero as a postamble. This state machine will call a serializer FSM for each word, after reading from RAM or generating the word value.

The serializer FSM loads the word it receives in a shift register, then waits for the 'get bit' signal from the write FSM. On the get bit request this FSM shifts out the bit from the shift register so it is available to the write FSM. If the last bit was shifted it, it signals that the word is emptied which triggers the higher level write field FSM to advance to its next word.

My first try at a write FSM was incorrect because I wrote it as if it were producing clock and data pulses, meaning go to 1 for 100 ns, then off for 200 to 500 ns. Wrong! A transition is just a knife edge change or toggle, so I had to rewrite it. Also, the write FSM must sit at 0 as its idle state value.

I built a good FSM to handle the write signals but ran out of time before testing today, as I have to get ready for dinner now. Tomorrow, I will test this, build the serializer and the overall write field FSMs.

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