Locking down the read bit stream performance for the Virtual 2315 Cartridge system

SYNCHRONIZING NEEDED TO KEEP STATE MACHINES ALIGNED

There are a number of state machines involved in generating the read bit streams. One covers the overall sector timing from the sector marker pulse, initial zero stream, sync word and then 321 20 bit data words. Another walks through the timing of the bit cells for each word, spitting out clocks and data pulses at the proper time, counting data bits that are 1 and producing the appropriate final four check bit cells of the word 

In addition there are machines that pull the next ram word and ready it for the machine timing each word. If the word isn't ready in time or arrives too early thus stepping on the value still being output, we would not have proper output. if the word machine doesn't begin at the proper point when each of the 321 words begins, we have distorted initial and final bit cell patterns. 

I worked out means to get this operating together rather than attempting to ensure that the individual word machine cycles perfectly to align with the sector machine defining the start of each word. The individual word machine waits to be triggered by the sector level machine, thus I could adjust the timing to get distortion free transitions. 

TWEAKED THE DURATION OF THE PULSES I WILL OUTPUT TO THE DRIVE

From some maintenance documents I uncovered, I found that the pulses produced by the read amplifier for each flux transition was shorter than the pulses I initially designed into my device. I adjusted the VHDL to make my pulses 200 nanoseconds long, which is in line with the scope images shown in the maintenance document. 

They must be long enough to trigger the drive circuits to emit a properly timed pulse out of the data separator. They also must be short enough to avoid false detection of 1 bits. With a bit cell of 1.4 us and a clock separator circuit that generates a 600 ns window to detect the data bit pulse, my original pulse width of 400ns might allow a clock pulse to slop over into the data bit window time. 

GOOD SIMULATION RESULTS WITH VERIFIED TIMING

The final simulation run showed me ideal results - the bit cells were all exactly 70 cycles long, or 1.4 microseconds, with the clock pulses all in the proper place and pulses for data bits of 1 exactly where they should be. 

I checked that the RAM addresses being requested were consistent with my scheme for storing the virtual cartridge images. I verified that the logic switched properly from sector to sector and wrapped around to zero after a rotation. 

Start of a sector - zeros, sync, words

zoom in on a few words

multiple sectors, sector marks at top