SIMULATION MODELING PROVIDED ONLY FOR VERILOG
The models that will accurately simulate the DDR3 memory interface I generated and permit me to verify that my driving logic is correct were built for Verilog based projects. Very approximately you can talk about hardware description languages as being in two camps. The government established VHDL as a standard and toolmakers support this language in order to participate in the funds that flow from defense projects. Various toolmakers promote an alternative, Verilog.
Xilinx is a toolmaker. Many hardware device makers are also aligned with the Verilog camp. The result is that the only simulation models that can be used for the DDR3 memory in the Xilinx toolchain are based on Verilog.
The simulation models have a handy parameter - SIM_BYPASS_INITIAL_CAL - which will turn off the modeling of the lengthy process by which the memory controller has to write and check all bits in order to adjust timings for the most reliable operation, as part of its initialization. This process is cumbersome and not practical for simulations, so they provide options such as FAST and NONE to speed up this stage and allow the designer to focus on their interaction with the memory controller and not on how the chips work internally.
This sounds great, but there is no method I can discover, either by myself or on the interwebs, where a VHDL based memory interface can access that parameter to modify it. Were I to have written the project in Verilog and implemented the memory interface in Verilog, I would be merrily debugging. But No! Not for you, lowly VHDL oriented designer.
Time to devise a workaround - either a dummy module to substitute for the memory or some other convoluted hacking of my code - since I really need to see waveforms to be comfortable that my read and write requests are set up properly. They have to happen in the right dance of interlocking signals, occur at the correct timing and with all the necessary setup and hold timing so that the memory will work properly.