Continued testing 1130MRAM board - retrigger redux

BOLSTERED GROUND CONNECTION OF THE TIMER CHIP

I added wires to increase the current capacity of the ground near the timer chip. I also bypassed the MOSFET that was included to isolate the board ground from the IBM 1130 until the +12V supply rail is present - to block backflow of current through gate inputs on my chips. 

ADJUSTED RC NETWORK SMOOTHING

I doubled the time constant of the RC network that should slow the edges of the pulses and absorb any very short glitches. I did this for the +Storage Read and +Storage Write signals that are what trigger the timers and could be the cause of the spurious retriggering. 

When I look at the effect of the smoothing filter, it cleans up the edges of the signal a bit and slows the rise but the noise in the center is unchanged, because I don't think it is coming in on the input but is instead being induced by something on my board.

WATCHED SIGNAL PATH FOR +STORAGE READ SIGNAL

I put one scope probe on the originating gate of +Storage Read in B-A1 slot J2 pin B13, another on B B1 slot E1 pin E11 where the cable enters compartment B1 after it leaves the source at compartment A1. It exits the compartment on B B1 H1 pin E11 and comes over cable T3 to my board where I hung a third scope probe at the signal as it entered the RC network on my board. The fourth probe was placed on the output of a NAND gate which combines +Storage Read and +Storage Use signals to produce a low output whose falling edge triggers the time. 

The waveforms were quite clean all the way through until the NAND gate. It is there that I see the sharp pulse right at the time of the retrigger. One theory is that something is wrong with the NAND gate causing the pulse. The two inputs stay high through the point of instability.

The yellow signal is +Storage Read and the green signal is the output of the NAND gate. At the bottom in blue is the pulse produced by the second read timer. Notice the sharp peak from the NAND, coming all the way up to 3.3V from 0 for perhaps 10 nanoseconds. 

 

WATCHING THE RETRIGGERING POINT ON THE SCOPE

The next experiment I did was to watch the relative timing between the different signals. Yellow monitored the VCC pin of the first read timer chip. Green is the bump in the NAND gate output when we have the retrigger. Purple is the ground pin of the first read timer chip and blue is the output of the second read timer chip. 

The impact on the NAND gate signal happens after the pulse rises from the second read timer chip. This suggests that the pulse is an early event in the chain leading to the retrigger. I then changed the scope probes slightly and watched again.

Blue is still the output pulse of the second read timer, while purple is the output of the first read timer chip. Its long 800ns pulse is ending which becomes the trigger for the second read timer chip. The green line is the pulse on the NAND gate. Relative timing is that the second chip pulse fires, whatever occurs drives the NAND output up and the retrigger happens about the same time. This is still not definitive for causality. 

DIGGING INTO POWER DELIVERY TO THE TIMER AND NAND CHIPS

I then moved on to the possibility that it is still an issue with the energy delivery rate from the 3.3V rail to the chips displaying problems. I had mentioned in earlier posts that when the word being read out has many bits on, the retriggering issue is noticeably worse than when reading a word of all zero bits. Each one bit being delivered sinks about 8ma of current from the IBM 1130 -Sense Bit x connections. 

I used an entire layer of the board as a ground plane, plus widened the 3.3V rail traces significantly. I believed this was over-engineering and rendered the PCB relatively safe from power rail sagging during gate switching. I decided to look closer to see whether there is any weakness that I hadn't considered, and I think I found it!

The yellow rectangles show the locations of the NAND chip and the two read timer chips. On the left side of the PCB you can see the wide traces for 3.3V delivery in red, but then the 3.3V wide trace is down on the bottom layer of the PCB. It may be wide, but look at where the power transitions from the top layer (red) to the bottom layer (blue). A single via with 15 mil diameter is what carries the power across the layers. 

That should support over one ampere if the via heats up 10 degrees over ambient, with just a few millivolts of voltage drop. Indeed my probes on the VCC pin of the timer chip shows that the 3.3 rail is pretty constant and does NOT dip down any appreciable amount. The decoupling capacitors for each chip will provide short term energy to the chip. 

Previously I had also watched the VCC and ground pins of the read timer chip without seeing much wiggle of the trace. I didn't watch the NAND gate however the retriggering problem existed before I began routing the +Storage Read signal through the NAND gate, thus I have to believe the spike I see on the NAND output is flowing back from the timer chip and not a deficiency in the gate itself. 

I will add some wires to the ground and VCC pins of the two read timer chips to bypass any chance that the power delivery is the problem leading to retriggering. Work for a future session in the shop. 

DIAGNOSING FAILURE OF WRITE

With all the changes, patches, bodge wires and resoldering attempts, the board will not trigger on +Storage Write anymore, thus I can't write new data patterns to do my testing. I put one scope lead on the output of the RC network for the signal, also serving as the scope trigger. a second probe on the Q output of the first write timer chip U12, a third probe on the Q output of the second write timer chip U13 and a fourth on the NAND gate that produces a logic low -W for the MRAM chip when the second timer chip pulses high and +Storage Write is still high. 

The scope trace showed me that the trigger is activating as it should but the first write timer chip is not triggering. I tested connectivity on the pins of the chip, which all appear to be working correctly. I didn't spot the cause by the time I had to leave the workshop, but I will keep working on this until I figure out why the chip, previously working properly, stopped sometime after I did some resoldering on the chips.