I woke up with coffee and Python this morning, extending the PC side program to use simh and IBM 1130 simulator files as the card images to be passed to the 1130 when it boots or reads from the virtual card reader. I had the boot method set up, but have not moved over all the code from my keypunch golem program that deals with the 1130 simulator file formats and conversions.
Over lunchtime I rolled in the formatting and checking routines from the keypunch program and tested them. I then began built code to translate all of this to its hollerith code equivalent which is how it will be passed down to the 1130 on each read.
I began on the FSM for the PC program that controls the virtual reader - deciding when to update status, store a card image into memory, handle the last card situation and other complexities. Because the 2501 reader, as with the 1442 reader, has a pre-read station into which a card is first moved before it is read on the next cycle, every feed cycle is reading the prior card while feeding the current one. If the hopper runs out of cards (we reach end of the PC file), that leaves the last card sitting in the pre-read station.
There are only two ways to read that last card. A new deck is put into the hopper (e.g. we open another PC file), or we take a special operator action that tells the adapter to do a cycle but mark the DSW with the 'last card' status. This is how the operator signals the end of a card deck, with the special last card sequence, otherwise any time the hopper runs out, we can place more cards from the same large deck into the machine in order to continue reading that deck.
In order to handle this behavior, I needed a check box called "Set Last Card" and a button labeled "NPRO". The purpose of NPRO is to throw away the card in the pre-read station, if you don't want it to be read. These were added at lunchtime as I worked on the virtual card reader FSM. The rest had to wait until early evening when I could get back to the 1130 project.
When I restarted in the evening, I did a bit of rearranging of how a virtual device would function between the PC and the fpga, when I saw that a few timing vulnerabilities existed when certain state was updated from the PC. I moved that logic to the fpga where it could operate in bounded time appropriate to the 1130's speed.
I also built up most of the data pump that works over the fast SPI link to synchronize input and output signals between the two boards. This should be put under test with a second fpga board by the weekend.
The part of the virtual 2501 card reader that read and prepared PC files to be shipped to the 1130 was completed and tested to some degree. I then worked on the FSM implementation so that I could process the card reading in chunks in between GUI handling. I initially set it to handle a chunk of work every 50 milliseconds, which should support reading cards in the range of hundreds of cards per minute. The target to match a 2501 is at least 600 CPM, which is easily attainable but will need tweaking of the timing between chunks of work in order to hit the right pace.
There are only two ways to read that last card. A new deck is put into the hopper (e.g. we open another PC file), or we take a special operator action that tells the adapter to do a cycle but mark the DSW with the 'last card' status. This is how the operator signals the end of a card deck, with the special last card sequence, otherwise any time the hopper runs out, we can place more cards from the same large deck into the machine in order to continue reading that deck.
In order to handle this behavior, I needed a check box called "Set Last Card" and a button labeled "NPRO". The purpose of NPRO is to throw away the card in the pre-read station, if you don't want it to be read. These were added at lunchtime as I worked on the virtual card reader FSM. The rest had to wait until early evening when I could get back to the 1130 project.
When I restarted in the evening, I did a bit of rearranging of how a virtual device would function between the PC and the fpga, when I saw that a few timing vulnerabilities existed when certain state was updated from the PC. I moved that logic to the fpga where it could operate in bounded time appropriate to the 1130's speed.
I also built up most of the data pump that works over the fast SPI link to synchronize input and output signals between the two boards. This should be put under test with a second fpga board by the weekend.
The part of the virtual 2501 card reader that read and prepared PC files to be shipped to the 1130 was completed and tested to some degree. I then worked on the FSM implementation so that I could process the card reading in chunks in between GUI handling. I initially set it to handle a chunk of work every 50 milliseconds, which should support reading cards in the range of hundreds of cards per minute. The target to match a 2501 is at least 600 CPM, which is easily attainable but will need tweaking of the timing between chunks of work in order to hit the right pace.
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