CHANGED SENSE OUTPUT DRIVER GATE TEMPORARILY
I am resigned to having to build another PCB in order to use a chip that has enough current sink capability to work with the 1130. I did set up components on a breadboard to redrive the signal for a couple of sense lines, to see if things work correctly with sufficient current sinking.
Since the current circuit is failing to set the B register, it is the same as when I store a 0 value for that bit. I will wire up the two check bits, as they must be on with an even parity such as all zeroes. I will also wire up bit 15 so that I can experiment with setting the word to either 0000 or 0001 which both should have correct parity when read back given the three circuits I will establish.
In order to use the existing board for this test, I just lifted the output pin of the three signals off of the 74HC03 chip where they were soldered. I can tack a wire to the pad and another to the lifted pin, interposing my ad hoc circuit between the two.
I used a 74HC04 inverter chip to convert the output of the 74HC03, an open collector that pulls to ground when the pulse should be generated, to a pulse that starts at 0V and goes up to the 3.3V level for a short period. This required a pull-up resistor on the input to the inverter, pulling it to 3.3V unless the open collector sinks down to ground for the pulse. The input to the inverter comes from the 74HC03 lifted output pin.
The output of the inverter was connected through a 720 ohm resistor to a 2n3904 NPN transistor. The emitter is connected to ground, the base connected through the 720 ohm resistor and the collector is hooked to the output for the -Sense bit line. This should be capable of sinking as much current as the SLT circuit can deliver - with the resistor I selected and the gain (beta) of the 2n3904, it could sink around 180ma which is why more than the 8-9ma I see in the LTSpice simulation as a minimum to flip and the 24ma it shows when the transistor is saturated.
TESTING WITH LOAD AND DISPLAY MODE
I did a load of memory with all zero bits, then did a display. This should return all zeroes plus the two parity check bits at 1, for a good read. This worked as expected, no parity stop. The pulse coming back from the sense outputs to the B register were nice and strong.
I then flipped bit 15 of the Console Entry Switches to 1 and loaded that value (x0001) to memory before doing another read. This should deliver x0001 to the 1130 with the first check bit at 1 and the second check bit at 0. That was exactly what I saw on the display panel and again no parity stop. The scope showed that the pulse was strong enough to definitively flip the B register bit on when we are outputting a pulse.
 |
| B reg in purple set by sense pulse in blue |
FIXING THE ISSUE PERMANENTLY
After I had validated the diagnosis that insufficient current sinking was the issue with the 74HC03 chips I had used on the prior design, I switched my design over to 74LCX38 chips that will sink 24ma per output, works on 3.3V VCC and is also a quad 2 input NAND open collector device.
While an SOIC-14 version of the 74LCX38 is identical in footprint to the 74HC03, it is effectively unavailable so I had to switch to the smallest TSSOP footprint as even the intermediate SOP version was effectively unavailable. That required me to redo the PCB which I completed and sent off to JLCPCB on October 3rd. I also ordered the new chips and other parts from Digikey to build the new PCB, which should arrive before the PCB.
